<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/56905>56905</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            Patch D129980 can cause infinite loop in DAG Combine
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            backend:RISC-V
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
            topperc
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          topperc
      </td>
    </tr>
</table>

<pre>
    This patch turns (seteq (i64 (and X, 0xffffffff)), C1) into (seteq (i64 (sext_inreg X, i32)), C1). If bit 31 of X is known to be zero, SimplifyDemandedBits will turn the sext_inreg back into an AND leading to an infinite loop.

This was introduced before the 15 branch will need to be fixed there
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJxtkE1vnDAQhn-NuYyCjFk2cPBhs6hVLlXVVFVulTEDTOO1qW26m_76GnartFWRZc8H4_fx27n-VX6eKMCsop4gLt4GYKIOGPH7GtB-tx7K9vDMxBH4Zbh9TDTbOsKxSAGQje5_owEv8StZj-P1BirFP6M5PA7QUYSyADfAMySeF-vOFtKNHcJP9G79-YlOs6HhtcVT4sH-gWKAMxmzcUOcEP4Q65R-uUIpC4cPLRhUPdkRrhWyA1mKCMa5OWe8Zfxw3Tc_ziqsw971i8Y-UQzO4yZRVNB5ZZNbm7TF1L5yDnRZ4wk9ZiiLfdVUO1HXu6yXZd-UjcoiRYPy4-Z1W4imqTnoBKPVEvBvpJRBe3gPR3fqyGK2eCOnGOfAygMT79IaKU5Ll2t3SokxP34fd7N331DHlFIIC4YUVPuGV9kki2KPmt9zrQdR7rpaqB4LLMXQ1FgPvM-M6tAEyaoHJsRqIdo-KX56fDrefUklVrUZScGF4DUvi_2650LxHUfkdV0Ntb5vWMpOiky-4uTOj5mXG1m3jCE1DYUY3poqBBqTjzfV6OYZvb6JqSVOzstbMdteJLfn_AKbJN7v">