<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/56872>56872</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            Useless copies of x0 (zero) to registers used in branch comparisons without ISel patterns explicitly selecting X0
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            backend:RISC-V,
            regalloc
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          asb
      </td>
    </tr>
</table>

<pre>
    See [D130809](https://reviews.llvm.org/D130809) for the patch to work around this in the RISC-V backend by adding additional ISel patterns. As noted by @topperc, the register coalescer doesn't always seem to succeed in doing this, when really it should.

Creating this issue to track the problem, as it would be nice to be able to remove these patterns at a later point if the problem can be identified and resolved.
</pre>
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