<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/56887>56887</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [AMDGPU][MC][GFX11] Lacking MC tests for several gfx11 instructions
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            backend:AMDGPU,
            mc
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
            dpreobra
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          Sisyph
      </td>
    </tr>
</table>

<pre>
    We have tests for the dpp versions of these instructions, but not the base _e32 or _e64 versions. 

These tests will be useful for catching regressions in planned work to support true16 instructions.
Currently, these instructions will not be emitted using registers above 127, but they can be assembled or disassembled with those high registers. The asm and disasm will be incorrect from the perspective of what the hardware will do. For example

Input:

    v_ceil_f16 v0, v255

Output:

    v_ceil_f16_e32 v0, v255                 ; encoding: [0xff,0xb9,0x00,0x7e]

True behavior of object code with 0xff,0xb9,0x00,0x7e :

    v_ceil_f16    v0.l, v127.h

VOP2:
v_mul_f16
v_min_f16
v_max_f16
v_ldexp_f16
v_add_f16
v_sub_f16

VOP1:
V_CVT_F16_U16
V_CVT_F16_I16
V_CVT_U16_F16
V_CVT_I16_F16
V_RCP_F16
V_SQRT_F16
V_RSQ_F16
V_LOG_F16
V_EXP_F16
V_SIN_F16
V_COS_F16
V_FREXP_MANT_F16
V_FREXP_EXP_I16_F16
V_FLOOR_F16
V_CEIL_F16
V_TRUNC_F16
V_RNDNE_F16
V_FRACT_F16
V_CVT_NORM_I16_F16
V_CVT_NORM_U16_F16
V_NOT_B16
V_CVT_I32_I16

@dpreobra Can you please help with creating the tests?
</pre>
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