<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/56735>56735</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [AMDGPU][MC][GFX11] DPP variants of v_fma_mix* opcodes accept SGPRs for src1
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            backend:AMDGPU,
            mc
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          dpreobra
      </td>
    </tr>
</table>

<pre>
    Assembler accepts only VGPRs for `src1` of DPP64 opcodes except for `v_fma_mix*` which may use SGPRs for `src1`.

An example of failed test:

    v_fma_mix_f32 v5, v1, s3, v4 dpp8:[7,6,5,4,3,2,1,0]

Expected output:

    An error.

Actual result:

    v_fma_mix_f32_e64_dpp v5, v1, s3, v4 dpp8:[7,6,5,4,3,2,1,0] ;
    encoding: [0x05,0x00,0x20,0xcc,0xe9,0x06,0x10,0x04,0x01,0x77,0x39,0x05]

I'm not sure if this is a bug because documentation is scarce. SP3 is more consistent in this respect - for all DPP64 opcodes it enables SGPRs for `src2` only.

Added @Sisyph and @jayfoad for awareness.

</pre>
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