<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/56645>56645</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            Possible improvement for SimplifyDemandedBits for Mul
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            llvm:optimizations
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          topperc
      </td>
    </tr>
</table>

<pre>
    If the RHS is a constant with X trailing zeros, then the X MSBs of the LHS are not demanded.

I don't have any plans to do anything with this right now. Just something I thought of while working on https://reviews.llvm.org/D130146 That patch does special isel for (i64 (mul (and X, 0xffffffff), 3 << C)) and requires C < 32. If C >= 32 the AND could be removed, but it doesn't happen today.

FYI @spatel-gh @RKSimon 
</pre>
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