<table border="1" cellspacing="0" cellpadding="8">
<tr>
<th>Issue</th>
<td>
<a href=https://github.com/llvm/llvm-project/issues/56512>56512</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>
[AMDGPU][MC][GFX11] Disassembly fails for *_e64_dpp opcodes which support op_sel
</td>
</tr>
<tr>
<th>Labels</th>
<td>
backend:AMDGPU,
mc
</td>
</tr>
<tr>
<th>Assignees</th>
<td>
dpreobra
</td>
</tr>
<tr>
<th>Reporter</th>
<td>
dpreobra
</td>
</tr>
</table>
<pre>
It looks like all opcodes which support `op_sel` in `VOP3` encoding have broken `_e64_dpp` and `_e64_dpp8` variants - they cannot be disassembled.
An example of a failed test:
0x05,0x00,0x03,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05
Expected output:
v_add_nc_u16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
Actual result:
Assertion failed: isImm() && "This is not an immediate"
The root cause of this issue is that these opcodes have `op_sel` operand which is not created by disassembler automatically and must be added manually.
A similar issue is being addressed in https://reviews.llvm.org/D129084, but it only affects 2 opcodes.
A fix is pending.
</pre>
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