<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/56414>56414</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [HIP] Compiling code for different AMD architectures
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          densamoilov
      </td>
    </tr>
</table>

<pre>
    DPC++ with HIP AMD backend requires to specify a target architecture via `-Xsycl-target-backend --offload-arch=gfx90a`.
This means that the code should be compiled for each architecture which may be a problem for libraries that have such code.

Is it possible to add support for AMD backend similar to CUDA via `-fsycl-targets=nvptx64-nvidia-cuda`? 
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJxVUU2PmzAQ_TVwGRE5fCThwCEbtOoeKu2hlXod8ADTGkxtk938-w5k025ly_bYb-a9eW6svlX16yVKn2TCG4cBvry8wvlrDQ22v2jS4Oj3wo48BAt-ppa7GyAEdD0FQNcOHKgNiyO4MkJ0UMkPf2tNckckjzJJYrvOWNTJmhNldd-9lwoFv4tUHanzt4E9jISTMA0YZCForSbwg12MhmYNx5kNaeisA8J2-J__bWC5GvG2YhFmZxtD4wY23Dh0TB-1B7xK3UXQK8OHgPv64oEDzNZ7luy1adRasPNsXdhqfTbH88gG3Qq7fK_Pfy3oPlngpdnpOof3Q55MV9aMSbvotfMoe4ZYV5kusxLjwMFQFRVP8gNRUcNl65an_m7DSq2568jRFDYRn5v38eJMNYQwC905Sp9l9vKdS7MT1yQw5vrYEnHmp6RJyN4v5OVQHPJ9Hg_VibKyLU86K09YHlLMVNoVp7wr9qRU22SxwYaMX2WKxpirVKWpOsqQPdvvjkinTOdqX5QqPxzzKFc0IpvdSryzro9dtWlolt7Lo2Ef_L9HFNv7iehRH5cwWFdpmjyOlo29xpvkatP7B-KW6WQ">