<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/56412>56412</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [AArch64][SVE] Error in masked_gather_v2f16 when enabling SVE for 128-bit target
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          MattPD
      </td>
    </tr>
</table>

<pre>
    Encountering an ICE after removing NEON preference in `useSVEForFixedLengthVectors` for 128-bit vector register size SVE code generation.

Context:
There's currently a `>= 256` vector size restriction in `useSVEForFixedLengthVectors` (in "llvm/lib/Target/AArch64/AArch64Subtarget.h").

```
bool useSVEForFixedLengthVectors() const {
  // Prefer NEON unless larger SVE registers are available.
  return hasSVE() && getMinSVEVectorSizeInBits() >= 256;
}
```

As an experiment I've relaxed it in two different ways, by changing the line in question to `return hasSVE() && getMinSVEVectorSizeInBits() >= 128;` or `return hasSVE();` (with the same effect).

I've then run the build of the modified compilier on the AArch64 LIT tests, encountering an ICE for the following test:
https://github.com/llvm/llvm-project/blob/main/llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll

Compilation using either `clang` or `llc` together with the assumed 128-bit SVE register size is sufficient to trigger the ICE:
```
clang -msve-vector-bits=128 -mcpu=neoverse-n2 sve-fixed-length-masked-gather.ll
llc -aarch64-sve-vector-bits-min=128 -mtriple=arm64-unknown-unknown -mcpu=neoverse-n2 sve-fixed-length-masked-gather.ll
```

This function alone is sufficient to trigger the ICE:
```
target triple = "aarch64-unknown-linux-gnu"

define void @masked_gather_v2f16(<2 x half>* %a, <2 x half*>* %b) vscale_range(2,0) #0 {
  %cval = load <2 x half>, <2 x half>* %a
  %ptrs = load <2 x half*>, <2 x half*>* %b
  %mask = fcmp oeq <2 x half> %cval, zeroinitializer
  %vals = call <2 x half> @llvm.masked.gather.v2f16(<2 x half*> %ptrs, i32 8, <2 x i1> %mask, <2 x half> undef)
  store <2 x half> %vals, <2 x half>* %a
  ret void
}

declare <2 x half> @llvm.masked.gather.v2f16(<2 x half*>, i32, <2 x i1>, <2 x half>)

attributes #0 = { "target-features"="+sve" }
```

Removing the `vscale_range(2,0)` attribute or changing it to `vscale_range(1,0)` has no impact (i.e., the ICE still occurs).

Here's the output from the ICE in question (note the cyclic pattern of function calls in SelectionDAG):
```
$ clang -msve-vector-bits=128 -mcpu=neoverse-n2 sve-fixed-length-masked-gather.ll

PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace, preprocessed source, and associated run script.
Stack dump:
0.      Program arguments: /llvm_build/bin/clang-15 -cc1 -triple aarch64-unknown-linux-gnu -emit-obj -mrelax-all --mrelax-relocations -disable-free -clear-ast-before-backend -main-file-name sve-fixed-length-masked-gather.masked_gather_v2f16.only.ll -mrelocation-model pic -pic-level 2 -pic-is-pie -mframe-pointer=non-leaf -fmath-errno -ffp-contract=on -fno-rounding-math -mconstructor-aliases -funwind-tables=2 -target-cpu neoverse-n2 -target-feature +v8.5a -target-feature +crc -target-feature +lse -target-feature +rdm -target-feature +crypto -target-feature +dotprod -target-feature +fp-armv8 -target-feature +neon -target-feature +fullfp16 -target-feature +ras -target-feature +sve -target-feature +sve2 -target-feature +sve2-bitperm -target-feature +rcpc -target-feature +mte -target-feature +ssbs -target-feature +sb -target-feature +bf16 -target-feature +i8mm -target-feature +fp16fml -target-feature +sm4 -target-feature +sha3 -target-feature +sha2 -target-feature +aes -target-abi aapcs -mvscale-max=1 -mvscale-min=1 -fallow-half-arguments-and-returns -mllvm -treat-scalable-fixed-error-as-warning -debugger-tuning=gdb -fcoverage-compilation-dir=/llvm_src -resource-dir /llvm_build/lib/clang/15.0.0 -fdebug-compilation-dir=/llvm_src -ferror-limit 19 -fno-signed-char -fgnuc-version=4.2.1 -fcolor-diagnostics -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /tmp/sve-fixed-length-masked-gather-a81266.o -x ir sve-fixed-length-masked-gather.masked_gather_v2f16.only.ll
1.      Code generation
2.      Running pass 'Function Pass Manager' on module 'sve-fixed-length-masked-gather.masked_gather_v2f16.only.ll'.
3.      Running pass 'AArch64 Instruction Selection' on function '@masked_gather_v2f16'
  #0 0x0000ffff784b83bc llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) /llvm_src/llvm-project/llvm/lib/Support/Unix/Signals.inc:573:3
  #1 0x0000ffff784b69f8 llvm::sys::RunSignalHandlers() /llvm_src/llvm-project/llvm/lib/Support/Signals.cpp:104:18
  #2 0x0000ffff784b6ba4 SignalHandler(int) /llvm_src/llvm-project/llvm/lib/Support/Unix/Signals.inc:407:1
  #3 0x0000ffff7d9216c0 (linux-vdso.so.1+0x6c0)
  #4 0x0000ffff7792dd60 llvm::DAGTypeLegalizer::AnalyzeNewNode(llvm::SDNode*) (.part.0) /llvm_src/llvm-project/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp:501:9
  #5 0x0000ffff7792dcf8 llvm::SDNode::getNodeId() const /llvm_src/llvm-project/llvm/include/llvm/CodeGen/SelectionDAGNodes.h:713:34
  #6 0x0000ffff7792dcf8 llvm::DAGTypeLegalizer::AnalyzeNewValue(llvm::SDValue&) /llvm_src/llvm-project/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp:572:31
  #7 0x0000ffff7792de08 llvm::SDValue::getNode() const /llvm_src/llvm-project/llvm/include/llvm/CodeGen/SelectionDAGNodes.h:151:36
  #8 0x0000ffff7792de08 llvm::DAGTypeLegalizer::AnalyzeNewNode(llvm::SDNode*) (.part.0) /llvm_src/llvm-project/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp:525:32
  #9 0x0000ffff7792dcf8 llvm::SDNode::getNodeId() const /llvm_src/llvm-project/llvm/include/llvm/CodeGen/SelectionDAGNodes.h:713:34
 #10 0x0000ffff7792dcf8 llvm::DAGTypeLegalizer::AnalyzeNewValue(llvm::SDValue&) /llvm_src/llvm-project/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp:572:31
 #11 0x0000ffff7792de08 llvm::SDValue::getNode() const /llvm_src/llvm-project/llvm/include/llvm/CodeGen/SelectionDAGNodes.h:151:36
 #12 0x0000ffff7792de08 llvm::DAGTypeLegalizer::AnalyzeNewNode(llvm::SDNode*) (.part.0) /llvm_src/llvm-project/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp:525:32
 #13 0x0000ffff7792dcf8 llvm::SDNode::getNodeId() const /llvm_src/llvm-project/llvm/include/llvm/CodeGen/SelectionDAGNodes.h:713:34
 #14 0x0000ffff7792dcf8 llvm::DAGTypeLegalizer::AnalyzeNewValue(llvm::SDValue&) /llvm_src/llvm-project/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp:572:31
 #15 0x0000ffff7792de08 llvm::SDValue::getNode() const /llvm_src/llvm-project/llvm/include/llvm/CodeGen/SelectionDAGNodes.h:151:36
. . .
#500 0x0000ffff7792de08 llvm::DAGTypeLegalizer::AnalyzeNewNode(llvm::SDNode*) (.part.0) /llvm_src/llvm-project/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp:525:32
#501 0x0000ffff7792dcf8 llvm::SDNode::getNodeId() const /llvm_src/llvm-project/llvm/include/llvm/CodeGen/SelectionDAGNodes.h:713:34
#502 0x0000ffff7792dcf8 llvm::DAGTypeLegalizer::AnalyzeNewValue(llvm::SDValue&) /llvm_src/llvm-project/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp:572:31
#503 0x0000ffff7792de08 llvm::SDValue::getNode() const /llvm_src/llvm-project/llvm/include/llvm/CodeGen/SelectionDAGNodes.h:151:36
#504 0x0000ffff7792de08 llvm::DAGTypeLegalizer::AnalyzeNewNode(llvm::SDNode*) (.part.0) /llvm_src/llvm-project/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp:525:32
#505 0x0000ffff7792dcf8 llvm::SDNode::getNodeId() const /llvm_src/llvm-project/llvm/include/llvm/CodeGen/SelectionDAGNodes.h:713:34
#506 0x0000ffff7792dcf8 llvm::DAGTypeLegalizer::AnalyzeNewValue(llvm::SDValue&) /llvm_src/llvm-project/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp:572:31
clang-15: error: unable to execute command: Segmentation fault (core dumped)
clang-15: error: clang frontend command failed due to signal (use -v to see invocation)
clang version 15.0.0 (https://github.com/llvm/llvm-project.git ac3e26bcffa29d3519f87be678ad09431a6bf6f2)
Target: aarch64-unknown-linux-gnu
Thread model: posix
InstalledDir: /llvm_build/bin
clang-15: note: diagnostic msg: Error generating preprocessed source(s) - no preprocessable inputs.
```

I'm wondering, would you happen to know whether SVE code generation for the targets with 128-bit SVE registers is meant to be supported--and, possibly, would modifying `useSVEForFixedLengthVectors` as above be the proper way to go about it or could there be any remaining checks that need to be changed, e.g., in `AArch64TargetLowering::useSVEForFixedLengthVectorVT` (<https://github.com/llvm/llvm-project/blob/6f4773f06428d16cb4716e9d1ba590d8c2ff7596/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp#L5628-L5630>)?
```
// Ensure NEON MVTs only belong to a single register class.
if (VT.getFixedSizeInBits() <= 128)
```

cc @paulwalker-arm @sdesmalen-arm @stevesuzuki-arm (in case it's relevant to <https://github.com/halide/Halide/pull/6781>)
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJzdWtly2zgW_RrlBUUWRUqU9OAHeVHHVUkm1fZ4Hl0gCErsgASHIGUrXz_nAqQ200knPV3Vju2SRQAEzr04d8GS6HR3cVMK3ZaNrPNyzXjJbq9uGM_wzGpZ6C2Vfrr51ydW1TKTtSyFZHnJRnHQGnn3cLPS9Sp_lukHWa6bzYMUja4NalmmazYO516SN2xri9HhOjfUs8m_SoaXmdCpZGtZypo3uS79UXA9Cpbu80oD1XMzirrn-w2GH4Uzw0RbA0ijdowTkFF0M4quWTiNadxuLDtELU1T54K6_nOgR-Gc2oWhUttiFK5UnuDzntdr2eDLclmLTTw5fLtrk8ZW-hu8NAoXJxIQNvdnHxOtFfsWgHCOHqCT0jRsNLt0bzHAWeGPfbYT4CajLZU0hikau7aa7HVrGK8l41ueK54o6fed1LJp65JtuEHrbqRRGOMP-m8-5iWKHY47aO62vMybHtCRfqMO1Gh2PSii-1waIpJ8rkCqAhPFbjFtW5oOxSE0AyOg5eZJszTPLKka9sR3GO-KJTsmNrxcE--ajWQqLy3h_ttiLmkeG03z-NfFATdJHEw62DLcY1ePh6e82Vg4hheSSYAWzflsd0KiVcnqtrTNkzZXKdOZfSg0xM0hv9BFlascM6dds45N7MPtPWsgp9WEHDBMMip6IdNK6SerIzTfm8imaSpDT5Yxa4BuEx-jEZM7QuOfV9X6DyvAKlGaCF7wvDy0sV2GqyvY5m-yPKG92UovI-J6yjLXK7j5gqc1B6raV-rUgElMa9igPYGVOTUjbQuFOT4oXylBD43G5FGLvb65MW0BlfWe5JjqzsZzw0ybZbnIiUZgByx-TVZBr0Nne-WcUdUiYF5BIjmfQQNAe9cYC-WiavG9lHoLo5JeGbI_KTxkYR7nVmXeWe9eAUX3IwBopSQeeV2gaVt-KfVT2f__KxAGrfJ-A1VlbencIVe6_HnlOafHnASMzAnur5e5FwSm2z5767Il13gEJJUZGfVW5ykbTQInwqMT4XEbZuOYzC-6CtkzzFFlZLDhEiNMOdnFcU24PFQmZNxbI7iSjzXmFrFiDpd8FTjfEAWnPnUqtlxZ6ErzlJ2Pd_WipENw6KBq4G0HO-hgfQvroRuS33aTiaJiWv73bOQeK_X3VdY6L_Mm5wrcr496QQMHBvKrFz1MArJt36na79gypGoLsheORsyjkM2PRMnHXQPq66WaEJkwveQ7O2gG1JcDEhHe72sZTtny5DzqdDyCDQ90_mPCdkKeiziEbXE8Om_A_qSFs-zIRUYwuyRDcNbhZZIjpEhD9I-ubX5wCQPGF_bt-Pl7n3iRFaLuFVKTx9yjIEe6D5x504XJszfHR28i0LFSs7youGhs4uMjW4DUnelj5nIwSQtkW-Y81r3vUzFqrNumahuW1brYv3wcsdF3qRsbGZnYCZULVgG3RLRFZNx7JCKuoRfvpJK26Hr5m43Cwz5oFE7Y3-bE3efnDzfLO2iiTQqolCOcr0HJStdWvz8cbXMEM6LDCuEcWVApVJt2aqm52bCEiy9NzYWkaUC-jTcF0jyEP6Pb2hXTmwiKWuS8QQUlGkbADTfd_Nw16ISlbVHt9Rb4zP58rvW65gUSxHVLaRlhZx3KR5upUEZgMwGrV288ZZ4QY-Z1fv5VB888CQV5OvkDOrdZnkdeyOsf8KmFTQQM89LcUGbqZbWU6F9JXnvcNF4ikd1Ij5QgIaRHSQmmCi1LSrq-M3EDUcTXpdr5hKM4APCQhUnFKpDQwwc62-IxdA-5wT-AKjLoSXoVfC1oSgzCiwCaMS8rMIIn6xq242VZ5SFdpzlDEnYNEntZqb0aeVsKO_SoLbGQMvq6tfSE4-YGPsMD75HApV5DyiDGAkPnOMBadsxZ79ShYM4ut3N_yocqRC2GipWRQ8V1Wgx3sqtA8IGaVDdgZTpUBV0gkdnOh-ogTTn4TqtUVo3jQWxwUAPF4MErxYOKonLyCViLDIpai2pQYUUzPIxJhlElQ6VJNixaPi8GwZAqskINDlBMBos3PHqlfFAdXB7g8ySHSVcCJYULFCDsM_nOowKXr4KunFYcHsVCb-9APHgjzy2cqBNyJOQsMJxHrzsztzYLgyHyG--J1yWFKC-V8KZINb2mpQKMsk6hxEwQ7_laeuKwfIDPqG0Idb7KEMcRWK1TpLoXXsyt290iI1yNp37gB-jbjvm9jjOHVeXk88cLZ9ImX5cQAxG2RgFcnvDIPNEFXp_4oT-20BVeTHO-LjVCHyk242mKZpD3-vHxt6urx_fLh5vH6_8sf1-Fj1er28fl3UenYE1CNHDb31tleXw-DmN4N-YhV6n_gmN04WHchYer070YVxl2lb-3pZ22CrEHQGerPmp_poKPvMSM1SinFS08bEurAuQHPw8tnHUBLXoFQb9mvu18K4HZZw4dkn1ugefXVhqzQxKNLC54DvCT4Wc2nyTzKBHMxnLE0mhpdsZ9-Yw1eWMj7b0L1_NDo5o_PWL2YQSF3ZBAdlk2bgmyJ9nL1OBkv-murSjHwLd_l_kzFYB9yJd9pAwYYTqL8Bkd4R6f4Y4X2XwIN3TounoPw1Vyv-X0M9B6TKKiTGMcTOhzfgQqPAeV8Ak7Gd7utv1_dTMJZoTjCEZ0DCNdhONY2C0dl7xsU6N9_CEzvgyeUXW0dMHLk-OXZ4swTZE5HxSLBPV-V8kPct2tx2zpEnh2X-Un-fQJJnVCjrtrV7R0Qs_9iteNH_yYCg4bM6eZ8qrHQZj6iZkGWM0sj2WansskTsjSQbTfESXo4TY93Zr8E0i75PZQMAyaejf-BkPNxpbUkyOg8beBfk_5D1y159rvyuK_U-GzkAQ5puDsXBAZnGrcwTpW-d-v8PGUiBHFRzjn38b5FtgeTkmo8EioxVugO_nw4FegOwkyfgN0J5zhr0Z3Eip6K3R_EVrfKt1fxNN_Ht19ht9-1yyaBi9czRtnvhXqhdv5BzLfAn3hd94g860gL3zNP4_5FucLV_Mr0P0tpPEW6K-Qxvf74ShidnuIvrQlbXDRSYB8loLOYIQuCixtqfJOrmmLzJ1-Z7xV9oxF0GEYbc7LdL_QHOzbHWxkNd2BKdO-Y3SUK5miBzussUtf6rel7d2tLZN0XWLb7XafDsK6LSvWbYjhxR87w_DXdAwiIhnGicgyHi7SaDpeZPNZIuPZnKfBYhKNeZxkcRbux-6uz0Cq10-IuxPqWvKU2R16al5pgyW-u1wBxnIF2a9zq59-1o-PLV5ok06d6P9hR44VZk0lN6Tn_WYX7SoNnbbM6dyLeXRMdqi3c56XVduYPqQOneHRbZCCPekytRc4aB_oSbcqZTvdsg2vKmmvspAe2NPG3XoYuBG1v_Hh9myNuxkxdBvC0GF-Ibk7x08kM26nRKYebdPaIyVtTJ6o3QGMvZKyIwV8_24UN4wneiupb0IEfVR0VYPvaMC1ptq2obNHOoq03ZNUtj0vd3SdjOd2C09spPhCZ4e8YaWEwh1ge3wpLVLpr323dUbAuq0-x6MP-slp1PqC1zE_3Hd3d0bR1c_ei4mzyWwWZUE8CefpOBbJZDaO5SIdJ3y6CNK5COHSpov43NO8fmHsFq6nl8B6mjD6MI0xnfiMgu6UOVq9cuBp74HdlIY28-09sI8P94bRlin0pzSdGGMaGN21UfJwTwY2YXqy5hnp5OHeB0Crs4H7UVf9_aj9ifcQw4Wgo_YKru2Jqy-0L10XVGIQCwquZLkvaORWmvZr-yV3RfaSneDwWXljT5Fr-ONtx9xvT9cGjtrGo_f9l6ql3eIV3I87tl-8Sy-idBEt-Lsmb5S8GE0v-2mYXuOBrndNrzsXACADu8JkkSWT5N-Jr2Rmx9cZnS2-a2t18fNnwNN4Mg7fbS5ms_lsMl_EfMbTeBEEkCMeT7OZyOBGMzRRHHNrSAzAfpdfhEEYBrMgDsNwHAa-TDmPp7PJhMdBJsYBFE6Gpnx7CULX63f1hcWQtGtDdyPACXOoBDPoaEP2_fO22ej64iNvms8YjdBeWKj_A04sVjo">