<table border="1" cellspacing="0" cellpadding="8">
<tr>
<th>Issue</th>
<td>
<a href=https://github.com/llvm/llvm-project/issues/56390>56390</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>
Repeatedly storing zero with compressed instructions
</td>
</tr>
<tr>
<th>Labels</th>
<td>
backend:RISC-V,
performance
</td>
</tr>
<tr>
<th>Assignees</th>
<td>
</td>
</tr>
<tr>
<th>Reporter</th>
<td>
preames
</td>
</tr>
</table>
<pre>
Noticed this while glancing at generated code in SPEC. We have numerous cases like:
```
23 bc 05 00 sd zero, 24(a1)
23 b8 05 00 sd zero, 16(a1)
23 b4 05 00 sd zero, 8(a1)
```
Key observation is that X0 is not a compressed register, and that's the sole thing forcing this sequence to use uncompressed instructions.
We could do something like the following:
```
c.li s0, 0
sd s0, 24(a1)
sd s0, 16(a1)
sd s0, 8(a1)
```
All of the stores are now compressible, so we've traded a bit of register pressure and a longer critical path for 4 bytes of space savings.
</pre>
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