<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/56092>56092</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [X86] Provide ability to tune for alderlake-p and alderlake-e cores
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            backend:X86
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          RKSimon
      </td>
    </tr>
</table>

<pre>
    There are cases where developers are specifically optimizing particular functions for just the fast or just the efficient alderlake cores, yet there is no way to specify this when tuning codegen, either to make use of specific tuning flags or more accurate scheduler models (either for optimal scheduling or llvm-mca analysis).There are even Alderlake SKUs that don't have any available e cores.

I don't expect the hidden AVX512 or other ISAs of the fast cores to be supported - just to be able to tune it properly (i.e. code will still run on either).

Related to Issue #56061
</pre>
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