<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/56036>56036</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [AMDGPU][GFX11] Incorrect src0 type of dpp and dpp8 variants of v_cvt_*_e64
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            bug,
            backend:AMDGPU,
            mc
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
            dpreobra
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          dpreobra
      </td>
    </tr>
</table>

<pre>
    These instructions should only accept VGPRs as src0, however SGPRs are accepted as well.
An example of failed test:

    v_cvt_f32_i32_e64_dpp v5, s1 dpp8:[0,0,0,0,0,0,0,0]

Expected result:

    an error

Actual output:

    [0x05,0x00,0x85,0xd5,0xe9,0x00,0x00,0x00,0x01,0x00,0x00,0x00]

Moreover, this bug results in incorrect decoding of valid code. 
An example of failed test:

    0x05,0x00,0x85,0xd5,0xe9,0x00,0x00,0x00,0x01,0x00,0x00,0x00

Expected output:

    v_cvt_f32_i32_e64_dpp v5, v1 dpp8:[0,0,0,0,0,0,0,0]

Actual result:

    v_cvt_f32_i32_e64_dpp v5, s1 dpp8:[0,0,0,0,0,0,0,0]

A fix is being tested.


</pre>
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