<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/55942>55942</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [RISCV] EXPENSIVE_CHECKS failure in CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            backend:RISC-V,
            crash
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          RKSimon
      </td>
    </tr>
</table>

<pre>
    I'm currently seeing this failure on an EXPENSIVE_CHECKS build. I haven't been able to bisect it but it appears to be very recent.

```
FAIL: LLVM :: CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll (1371 of 19913)
******************** TEST 'LLVM :: CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll' FAILED ********************
Script:
--
: 'RUN: at line 2';   e:\llvm\ninja\bin\llc.exe -O2 -mtriple riscv64 -mattr=+v,+m,+zbb -riscv-enable-subreg-liveness < E:\llvm\llvm-project\llvm\test\CodeGen\RISCV\early-clobber-tied-def-subreg-liveness.ll      | e:\llvm\ninja\bin\filecheck.exe E:\llvm\llvm-project\llvm\test\CodeGen\RISCV\early-clobber-tied-def-subreg-liveness.ll
--
Exit Code: 2

Command Output (stdout):
--
$ ":" "RUN: at line 2"
$ "e:\llvm\ninja\bin\llc.exe" "-O2" "-mtriple" "riscv64" "-mattr=+v,+m,+zbb" "-riscv-enable-subreg-liveness"
# command stderr:

# After Greedy Register Allocator
********** INTERVALS **********
V0 [224e,224d:1)[448r,480r:0) 0@448r 1@224e
V1 [224e,224d:0) 0@224e
V2 [224e,224d:0) 0@224e
V3 [224e,224d:0) 0@224e
V4 [224e,224d:0) 0@224e
V5 [224e,224d:0) 0@224e
V6 [224e,224d:0) 0@224e
V7 [224e,224d:0) 0@224e
V8 [224e,224d:0) 0@224e
V9 [224e,224d:0) 0@224e
V10 [224e,224d:0) 0@224e
V11 [224e,224d:0) 0@224e
V12 [224e,224d:0) 0@224e
V13 [224e,224d:0) 0@224e
V14 [224e,224d:0) 0@224e
V15 [224e,224d:0) 0@224e
V16 [224e,224d:0) 0@224e
V17 [224e,224d:0) 0@224e
V18 [224e,224d:0) 0@224e
V19 [224e,224d:0) 0@224e
V20 [224e,224d:0) 0@224e
V21 [224e,224d:0) 0@224e
V22 [224e,224d:0) 0@224e
V23 [224e,224d:0) 0@224e
V24 [224e,224d:0) 0@224e
V25 [224e,224d:0) 0@224e
V26 [224e,224d:0) 0@224e
V27 [224e,224d:0) 0@224e
V28 [224e,224d:0) 0@224e
V29 [224e,224d:0) 0@224e
V30 [224e,224d:0) 0@224e
V31 [224e,224d:0) 0@224e
X10 EMPTY
%0 [16r,32r:0) 0@16r  weight:INF
%1 [32r,64r:0) 0@32r  weight:4.629630e-03
%3 [80r,96r:0) 0@80r  weight:INF
%4 [96r,112r:0) 0@96r  weight:INF
%5 EMPTY  weight:2.604167e-03
%6 [128r,144r:0) 0@128r  weight:INF
%7 [144r,160r:0) 0@144r  weight:INF
%9 [176r,192r:0) 0@176r  weight:INF
%10 [192r,208r:0) 0@192r  weight:INF
%12 [240r,256r:0) 0@240r  weight:INF
%13 [256r,288r:0) 0@256r  weight:4.629630e-03
%16 [320r,336r:0) 0@320r  weight:INF
%17 [336r,352r:0) 0@336r  weight:INF
%18 [352r,416r:0) 0@352r  weight:4.310345e-03
%20 [384r,400r:0) 0@384r  weight:INF
%21 [400r,416r:0) 0@400r  weight:INF
%22 [416e,448r:0) 0@416e  weight:4.665127e-03
%25 [64r,160r:0)[160r,208r:1)[208r,288r:2)[288r,480e:3)[480e,592r:4) 0@64r 1@160r 2@208r 3@288r 4@480e  L000000000000000C [64r,480e:1)[480e,592r:0) 0@480e 1@64r  L0000000000000030 [160r,592r:0) 0@160r  L00000000000000C0 [208r,592r:0) 0@208r  L0000000000000300 [288r,592r:0) 0@288r  weight:1.077586e-02
%26 [560r,576r:0) 0@560r  weight:INF
%27 [576r,592r:0) 0@576r  weight:INF
%28 [216r,288r:0)[288r,480e:1)[480e,592r:2) 0@216r 1@288r 2@480e  L0000000000000300 [288r,592r:0) 0@288r  L00000000000000C0 [216r,592r:0) 0@216r  L0000000000000030 [216r,592r:0) 0@216r  L000000000000000C [216r,216d:0)[480e,592r:1) 0@216r 1@480e  weight:7.809278e-03
%29 [64r,160r:0)[160r,208r:1)[208r,216r:2) 0@64r 1@160r 2@208r  L00000000000000C0 [208r,216r:0) 0@208r  L0000000000000030 [160r,216r:0) 0@160r  L000000000000000C [64r,216r:0) 0@64r  weight:1.097826e-02
%30 EMPTY  L000000000000000C [216r,280r:0) 0@216r  L0000000000000030 [216r,280r:0) 0@216r  L00000000000000C0 [216r,280r:0) 0@216r  weight:4.353448e-03
%31 [280r,288r:0)[288r,480e:1)[480e,488r:2) 0@280r 1@288r 2@480e  L000000000000000C [280r,280d:0)[480e,488r:1) 0@280r 1@480e  L0000000000000030 [280r,488r:0) 0@280r  L00000000000000C0 [280r,488r:0) 0@280r  L0000000000000300 [288r,488r:0) 0@288r  weight:9.967105e-03
%32 [488r,592r:0) 0@488r  L0000000000000300 [488r,592r:0) 0@488r  L00000000000000C0 [488r,592r:0) 0@488r  L0000000000000030 [488r,592r:0) 0@488r  L000000000000000C [488r,592r:0) 0@488r  weight:4.007936e-03
%33 [112r,120r:0) 0@112r  weight:INF
%34 [456r,480r:0) 0@456r  weight:INF
%35 [216r,220r:0) 0@216r  L00000000000000FC [216r,220r:0) 0@216r  weight:INF
%36 [276r,280r:0) 0@276r  L00000000000000FC [276r,280r:0) 0@276r  L0000000000000300 [276r,276d:0) 0@276r  weight:INF
RegMasks:
********** MACHINEINSTRS **********
# Machine code for function _Z3foov: NoPHIs, TracksLiveness, TiedOpsRewritten, TracksDebugUserValues
Frame Objects:
  fi#0: id=2 size=8, align=8, at location [SP]
  fi#1: id=2 size=64, align=8, at location [SP]

0B      bb.0.entry:
16B       %0:gpr = LUI target-flags(riscv-hi) @__const._Z3foov.var_49
32B       %1:gpr = ADDI %0:gpr, target-flags(riscv-lo) @__const._Z3foov.var_49
48B       dead $x0 = PseudoVSETIVLI 2, 73, implicit-def $vl, implicit-def $vtype
64B       undef %29.sub_vrm2_0:vrn4m2nov0 = PseudoVLE16_V_M2 %1:gpr, 2, 4, implicit $vl, implicit $vtype
80B       %3:gpr = LUI target-flags(riscv-hi) @__const._Z3foov.var_48
96B       %4:gpr = ADDI %3:gpr, target-flags(riscv-lo) @__const._Z3foov.var_48
112B      %33:vr = PseudoVLE8_V_M1 %4:gpr, 2, 3, implicit $vl, implicit $vtype
120B      PseudoVSPILL_M1 %33:vr, %stack.0 :: (store unknown-size into %stack.0, align 8)
128B      %6:gpr = LUI target-flags(riscv-hi) @__const._Z3foov.var_46
144B      %7:gpr = ADDI %6:gpr, target-flags(riscv-lo) @__const._Z3foov.var_46
160B      %29.sub_vrm2_1:vrn4m2nov0 = PseudoVLE16_V_M2 %7:gpr, 2, 4, implicit $vl, implicit $vtype
176B      %9:gpr = LUI target-flags(riscv-hi) @__const._Z3foov.var_45
192B      %10:gpr = ADDI %9:gpr, target-flags(riscv-lo) @__const._Z3foov.var_45
208B      %29.sub_vrm2_2:vrn4m2nov0 = PseudoVLE16_V_M2 %10:gpr, 2, 4, implicit $vl, implicit $vtype
216B      undef %35.sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5:vrn4m2nov0 = COPY %29.sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5:vrn4m2nov0
220B      PseudoVSPILL4_M2 %35:vrn4m2nov0, %stack.1, $x0 :: (store unknown-size into %stack.1, align 8)
224B      INLINEASM &"" [sideeffect] [attdialect], $0:[clobber], implicit-def dead early-clobber $v0, $1:[clobber], implicit-def dead early-clobber $v1, $2:[clobber], implicit-def dead early-clobber $v2, $3:[clobber], implicit-def dead early-clobber $v3, $4:[clobber], implicit-def dead early-clobber $v4, $5:[clobber], implicit-def dead early-clobber $v5, $6:[clobber], implicit-def dead early-clobber $v6, $7:[clobber], implicit-def dead early-clobber $v7, $8:[clobber], implicit-def dead early-clobber $v8, $9:[clobber], implicit-def dead early-clobber $v9, $10:[clobber], implicit-def dead early-clobber $v10, $11:[clobber], implicit-def dead early-clobber $v11, $12:[clobber], implicit-def dead early-clobber $v12, $13:[clobber], implicit-def dead early-clobber $v13, $14:[clobber], implicit-def dead early-clobber $v14, $15:[clobber], implicit-def dead early-clobber $v15, $16:[clobber], implicit-def dead early-clobber $v16, $17:[clobber], implicit-def dead early-clobber $v17, $18:[clobber], implicit-def dead early-clobber $v18, $19:[clobber], implicit-def dead early-clobber $v19, $20:[clobber], implicit-def dead early-clobber $v20, $21:[clobber], implicit-def dead early-clobber $v21, $22:[clobber], implicit-def dead early-clobber $v22, $23:[clobber], implicit-def dead early-clobber $v23, $24:[clobber], implicit-def dead early-clobber $v24, $25:[clobber], implicit-def dead early-clobber $v25, $26:[clobber], implicit-def dead early-clobber $v26, $27:[clobber], implicit-def dead early-clobber $v27, $28:[clobber], implicit-def dead early-clobber $v28, $29:[clobber], implicit-def dead early-clobber $v29, $30:[clobber], implicit-def dead early-clobber $v30, $31:[clobber], implicit-def dead early-clobber $v31
240B      %12:gpr = LUI target-flags(riscv-hi) @__const._Z3foov.var_44
256B      %13:gpr = ADDI %12:gpr, target-flags(riscv-lo) @__const._Z3foov.var_44
272B      dead $x0 = PseudoVSETIVLI 2, 73, implicit-def $vl, implicit-def $vtype
276B      %36:vrn4m2nov0 = PseudoVRELOAD4_M2 %stack.1, $x0 :: (load unknown-size from %stack.1, align 8)
280B      undef %31.sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5:vrn4m2nov0 = COPY %36.sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5:vrn4m2nov0
288B      %31.sub_vrm2_3:vrn4m2nov0 = PseudoVLE16_V_M2 %13:gpr, 2, 4, implicit $vl, implicit $vtype
304B      $x0 = PseudoVSETIVLI 2, 73, implicit-def $vl, implicit-def $vtype
320B      %16:gpr = LUI target-flags(riscv-hi) @__const._Z3foov.var_40
336B      %17:gpr = ADDI %16:gpr, target-flags(riscv-lo) @__const._Z3foov.var_40
352B      %18:vrm2 = PseudoVLE16_V_M2 %17:gpr, 2, 4, implicit $vl, implicit $vtype
368B      $x0 = PseudoVSETIVLI 2, 73, implicit-def $vl, implicit-def $vtype
384B      %20:gpr = LUI 1048572
400B      %21:gpr = ADDIW %20:gpr, 928
416B      early-clobber %22:vr = PseudoVMSBC_VX_M2 %18:vrm2, %21:gpr, 2, 4, implicit $vl, implicit $vtype
432B      $x0 = PseudoVSETIVLI 2, 9, implicit-def $vl, implicit-def $vtype
448B      $v0 = COPY %22:vr
456B      %34:vr = PseudoVRELOAD_M1 %stack.0 :: (load unknown-size from %stack.0, align 8)
480B      early-clobber %31.sub_vrm2_0:vrn4m2nov0 = PseudoVSEXT_VF2_M2_MASK %31.sub_vrm2_0:vrn4m2nov0(tied-def 0), %34:vr, $v0, 2, 4, 0, implicit $vl, implicit $vtype
488B      %32:vrn4m2nov0 = COPY %31:vrn4m2nov0
560B      %26:gpr = LUI target-flags(riscv-hi) @var_47
576B      %27:gpr = ADDI %26:gpr, target-flags(riscv-lo) @var_47
592B      PseudoVSSEG4E16_V_M2 %32:vrn4m2nov0, %27:gpr, 2, 4, implicit $vl, implicit $vtype
608B      PseudoRET

# End machine code for function _Z3foov.

*** Bad machine code: No live subrange at use ***
- function:    _Z3foov
- basic block: %bb.0 entry (0x196a8313d28) [0B;624B)
- instruction: 480B     early-clobber %31.sub_vrm2_0:vrn4m2nov0 = PseudoVSEXT_VF2_M2_MASK %31.sub_vrm2_0:vrn4m2nov0(tied-def 0), %34:vr, $v0, 2, 4, 0, implicit $vl, implicit $vtype
- operand 1:   %31.sub_vrm2_0:vrn4m2nov0(tied-def 0)
- interval:    %31 [280r,288r:0)[288r,480e:1)[480e,488r:2) 0@280r 1@288r 2@480e  L000000000000000C [280r,280d:0)[480e,488r:1) 0@280r 1@480e  L0000000000000030 [280r,488r:0) 0@280r  L00000000000000C0 [280r,488r:0) 0@280r  L0000000000000300 [288r,488r:0) 0@288r  weight:9.967105e-03
- at:          480B
LLVM ERROR: Found 1 machine code errors.
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace.
Stack dump:
0.      Program arguments: e:\\llvm\\ninja\\bin\\llc.exe -O2 -mtriple riscv64 -mattr=+v,+m,+zbb -riscv-enable-subreg-liveness
1.      Running pass 'Function Pass Manager' on module '<stdin>'.
2.      Running pass 'Verify generated machine code' on function '@_Z3foov'
 #0 0x00007ff65f2093f5 HandleAbort E:\llvm\llvm-project\llvm\lib\Support\Windows\Signals.inc:418:0
 #1 0x00007fff61ac1881 (C:\Windows\System32\ucrtbase.dll+0x71881)
 #2 0x00007fff61ac2851 (C:\Windows\System32\ucrtbase.dll+0x72851)
 #3 0x00007ff65f12eb80 llvm::report_fatal_error(class llvm::Twine const &, bool) E:\llvm\llvm-project\llvm\lib\Support\ErrorHandling.cpp:123:0
 #4 0x00007ff65e3c8b1e `anonymous namespace'::MachineVerifierPass::runOnMachineFunction E:\llvm\llvm-project\llvm\lib\CodeGen\MachineVerifier.cpp:309:0
 #5 0x00007ff65e26afd5 llvm::MachineFunctionPass::runOnFunction(class llvm::Function &) E:\llvm\llvm-project\llvm\lib\CodeGen\MachineFunctionPass.cpp:73:0
 #6 0x00007ff65e709b54 llvm::FPPassManager::runOnFunction(class llvm::Function &) E:\llvm\llvm-project\llvm\lib\IR\LegacyPassManager.cpp:1430:0
 #7 0x00007ff65e709f80 llvm::ilist_iterator<llvm::ilist_detail::node_options<llvm::Function,1,0,void>,0,0>::operator++ E:\llvm\llvm-project\llvm\include\llvm\ADT\ilist_iterator.h:157:0
 #8 0x00007ff65e709f80 llvm::FPPassManager::runOnModule(class llvm::Module &) E:\llvm\llvm-project\llvm\lib\IR\LegacyPassManager.cpp:1475:0
 #9 0x00007ff65e70a257 `anonymous namespace'::MPPassManager::runOnModule E:\llvm\llvm-project\llvm\lib\IR\LegacyPassManager.cpp:1545:0
#10 0x00007ff65e7097a7 llvm::legacy::PassManagerImpl::run(class llvm::Module &) E:\llvm\llvm-project\llvm\lib\IR\LegacyPassManager.cpp:536:0
#11 0x00007ff65c1fe9ed compileModule E:\llvm\llvm-project\llvm\tools\llc\llc.cpp:732:0
#12 0x00007ff65c202d7e main E:\llvm\llvm-project\llvm\tools\llc\llc.cpp:417:0
#13 0x00007ff65fecbd88 invoke_main D:\a\_work\1\s\src\vctools\crt\vcstartup\src\startup\exe_common.inl:78:0
#14 0x00007ff65fecbd88 __scrt_common_main_seh D:\a\_work\1\s\src\vctools\crt\vcstartup\src\startup\exe_common.inl:288:0
#15 0x00007fff63cd7034 (C:\Windows\System32\KERNEL32.DLL+0x17034)
#16 0x00007fff642c2651 (C:\Windows\SYSTEM32\ntdll.dll+0x52651)

error: command failed with exit status: 2147483651
$ "e:\llvm\ninja\bin\filecheck.exe" "E:\llvm\llvm-project\llvm\test\CodeGen\RISCV\early-clobber-tied-def-subreg-liveness.ll"
# command stderr:
FileCheck error: '<stdin>' is empty.
FileCheck command line:  e:\llvm\ninja\bin\filecheck.exe E:\llvm\llvm-project\llvm\test\CodeGen\RISCV\early-clobber-tied-def-subreg-liveness.ll

error: command failed with exit status: 2

--

********************
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90..
********************
Failed Tests (1):
  LLVM :: CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll
```
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJztPNty4ri2X0O_qKAsydeHPCSEzFBDulMhkz1zXihjC-LdxqZsk-7sr99rSfIVSBynM3Xq1El1G1to3S9akizWafhyMR8xZ0eCQ5aJpIhfSC5ElGxJ8RTlZONH8SETJE2In5DZX3ezr8v542w1_X02_WNJ1ocoDidkTp78Z5EAnoKshYC-61iQIiXrKBdBQSJoPsgPf78XfpbL7wR5FtkLyUQAdCcj43pkXOqrbeh_8vHmcr4Y8UuyWDzeErjB-2kait-Q5M39fDl9hE_AG7-Mgzhdr0U2LiIRjkOxGeeHdSa24zgCBkWeT-KYjJhLuUNJuiHU8ygfMU_TZcP_kYfZ8gFQO7-IS8BEUPDZNfkIW0qwZZBF-wKZko_jsZYXWAQ6939-xTu_IHGUCMKgacSvCCECIaxpHD_v4COJkn_78LmOEtkYTMRPQcbfGBnvCsAPJs-iPHi2TWjwiyIb8esRu3oesSl87NTHf9ZrMpbdxiJBN-mKDqqbklmLMH6M91n6b_ClurUQOT6VKramSsXWtL8jyL-RM31V0E0Ui-BJBN-luP8MZ20zzX5C5CA2tBJrBso03e38JCTfDsUeAgwcOy_C9FCgRx8Zm5nQgWE7Y3h3bHbW6tnD-hoT-EB5pz1BP2p_qL58xSvKPq_5RoNDTgItO0gssqwSt-5wuSlERn7LhAhfyL3YRjk-X8ZxGvhFmvUJeTL_-jC7f7xcLN8KQons0SAj64oxE-SfwkcIXFG0hXVlmm4GjaZrIKsGNBJjZBrYTCjcSCCFhB4jqfo3urF-3Xi_bma_bla_bna_bk6_bm6_bl6_bvSEkU7262kH2tMQtKclaE9T0J62oD2NQXtag_Y0B-1pD9bTHqxvXPS0B-tpD9bTHqynPVhPe7Ce9mA97cF62oP3tAfvZ4-_IN5mt3cPf5f51pL4qY3pkLNWNoRGQn6IaPuEtcr8600FI2lhbza1zRYMNDZgzInNPJsbYmzwClgaGhMvm3p2CxgazxCURvckk5S2ufTOcmkpSRvfsoltmNR2WvxIB6BMDgjUbIuDzWewS3-Q_QHMbo8j2HwGTJqdOkoUr6Nw57zGlZk8qXNmuG04j52FU-FnSnWDrC04bD4Hp8LRknwyt00Pm9-ysspznEnCnNsdLzlPWOpVAgCc1VYQNp-Dk3EnAWBcpx16VsctOTW4abUYVomPu9KgptE2KDafIawSoQQ4JozN5-CkZQAAA1bWI004aG5r2AZTtv1WZTi764Aymo2Gm-iSRz5VtmS60S3rICwvuS6O8IlNLeWdZskTUJK1EWKH8hTcADASjjeAhZjINkASsjDaf9OaT02IniJUC49YqKbYxcZ1vpISdiEla12IqcqgSvwuhJShA8ENBeGehnBbKYFODMexXBtMw2rTSOe3NJNO2ycs-7xPSOe3VHboErbOZwc96NButB5Z-KTiWSUaZnxaysjOGLSPek6bgJ6US1I9beb3QCg3K3VA7bDWQVtceiSukrLSrDNxDY85bjvavEHRpvIBez2GXvVY1kkpJyFaUdGFOBkVzajsAthmx8M9x2VtD-dGObi-aobO_OptU_eCmL4N0cz1Fof02i5BVLGkipD-8WLWuVP7utEjXkqVlNSMY8_UiOkR4pP4tMIUPrM7NrvnU2B_iHaMH0O0UqA38WyHGu3hlKvh7XSSME8kCU3yHRBarPdA8HdDKOO9CtHwNcNwPG63FSErKVm1QuZgnUKRnq3cuKx5TVWBHS1UWGfHAm41g4P1CKeb6ZsQpympqZNzOgyd85T6Q5R-qCEcOzyGOObtXmxv_fx7Xq9Cvb6sdHs5_X3-dTb_uny477e0hAtat37whCt1QRoKskkzsjkkQRGlCVn9D9-k6TOQJ1_Tu9_nOfBOHjI_-J4vqrUzaIlE-G2f34sfWVQUuC5d9roW68P2z1xkj358ELled8_8nSDf1ri6WYtGyCYCbgwkFoF2rhnJo_9A7rp2EZ8fR9ukeiiIXG1DHkGry7uRdd3CQo-x4HJhbzTqalyppdz1emJMRFJkLxW31NbfEZx5QvN2nxHASxZ_zknhZ1tRjDexvwX9uGrp8SlCa4OxV6sgTfJiopU7efazlal3CjhroKUNtJfX1_MGKeT-JJU47UHFdEsqofBDQGv-NCSVu1wcwvRxOXuYPy7muHQ7JQ7Ha7Tbx1EQFbiwjADP8cnW4mWv5-e2WdI4JOpbqDwm-WG9es52bIVyPGeJuWNJ-twivphRe_W4umUNFSAtyYzZpHrMR4cH12hok3_cSK5C6zVtb54wEv-QkTQVyKhXNfNc6qutJxfVRBtMVGri71IT5HJNqbT_3Xyx0Kg1ZQSHp7yAqJ4Y5T6U3BhIMwE2_p6kP5IxxhqJkiJtdK7CjrjVjhhlbi2c_XHL2BqtadZonROWsT9kmZKKbdRUmk5N-zm18yGnpo5dU_c-rjpLo_Ua7kaNE7rzPqQ7TQaK_tO6Yz0TgvEh5bEqb1dZiVslE3RlrKpbWt-y-pbXt2Z9ax3zPv1293dbxF-EXctxMmRNrSTeAWnGLlVPKuP3DmJ6KogZK6Nt_nUBZcfl8hYgbNxNU2tCeRQKsdnITcxrbPCLIoz8WDVoRtCg8JXevdTtrYFFDlKtPU5pVS2XSYciKFXBhiJgGgEfioBrBOZQBKZGYA1FYGkE9lAEtkbgDEXgaATuUASuRuANReCVjjTYFWnli8OdsfRGOtgdaemPdLBD0tIj6WCXpKVP0sFOSUuvpIPdkpZ-SQc7Ji09kw52TVr6Jh3snLT0TjbYO1npnWywd7IqVw5PlqV3ssHeyUrvZIO9k5XeyQZ7Jyu9kw32TlZ6Jxvsnaz0TjbYO1npnWywd7LSO_lg7-Sld_LB3gmQqiAxG4W5zKMfrI1NjddqlNy0OZEsa-OS2MDiuKTjlDX4583LWXP6wO2zVff9bPHt8rqsKF-pHeMUWG2Vjpss3b1VOlZT87oOp59Zh3P7c-pwtzGdqSVgK95zOtNYKhgwneFGPd_9BF_hrBlPv2CarrXGeTOeTs3T6ccm6iUdqzmndaVJduy8MT42Mee2-6nGcBtrG6y75EgN07Ucva1lGs0Fiu4y4r-aCJCox_SSk1nNjrs51mLsaAHqdnk1XT3-VSqvVK-ebbKPLd2ZnPVSpjdIl6bZMFV3xq4k1R2bmZ-bRzpQWVIvlR0vjr2VG0-ujZlVbjyyQjPDnF9BXc7-elg93jCwzOr2cvnH65DAZvnGMJGbecp-Wlid8dVku7aj8T5jtrLkiZWeKkvTEznWai23vS8LyWzgaDzNkY-dyjqsd9Zp4a1Wzkr9L2e_mc3E0hG5jJCPpRu7WklTZO9nD903lWdJSHZvbe60T0hUW0lXfhtW7QERfGWa4OvTfrIVuIFyyAXp7CmNKxoIBH_lNpL-du3nUUDWcRp8V3Fi4QYLkRssGDXGT-rZvsspD7FEle8rGFcjfmUz86oKkzGJIO9nh4pQFTf_V8JmTNK9yPBddKoU-T6GKi0VInv2Y22L_39p4NNfGhhDXGhtqz_0TPWVPMQzu7__do8dbtIDGrcdoyLL0izXUXm3mF0uZxhwOzzlRNaHLcnEPs0KPOr0VBR7uYHKbuDfNiqeDutJkO7gQZ6uUB_VQRJ2E-U57sKyG4JeFSVBfACKxROQzvz8CSIz-F5kfiA0-SWOUiQ87PbVxqcx0UknS7eZvyOQJg87CF3kozzvUp_uaBzwqM54fOIhH72VoVm8PyQJnjjb-3j8hzk3Zea7w4ZbP_G3MM1kDp5C26XhIcZMBkl5mhchcMpn8KQVwc6gfBRZtHkhW6Ce-YXopEyFukq4iBwKVp0MmR4-CG56E-MnOp6z2djWhhke31jkd7BRLC7XaOw-x4PiaA3X5WGP7gF3_4qSMP2RYxsUGH6cT8DggEetZxk1dVpT39jUD6jrYj3jThXRBp6XvBA7GM2s6SHICsjjYhLikbIr46eDUFXaQbSsg5a51gC0CNVCy1u6okysXYNIFciyS0XHauMXfrySsQQkgxjtVXd6-KFsBAMIGanFmHWaxhjhQzQ9QzLSXOAbk2CP0ULlMldDy2aTb8EDd03B32zDT9LkZZcecpL4O5HvIfpGalmIX-o3M6SXRSJDv9VSHpJvif62cuv-rNdHyDoUNPPc8NrMWy3mme1vQquhzw4nHT7L5hOGuKljw36f9o9EaBLXYjgdE9gtKRzDW1tmk5k7hC3zwifzP7-Hy0Js_eClQbV0HrWe1mDd6bK-aXl9FEd5sYoKzELg8Xza_SoUhR_FqiUB1a3SPfKdt7rWgk5x1QarlecU36KZ6ScDb2VXWZkgKQYV2VUvufVwUzdcXj9gc4v1yROKL7fIG9K7r0t_znC3MqmfMNttme1_rdEcq82212Hbl4ct3gj5V2X5ZbxaZoNXHAOMrood32loLJaI1H0D3Rwq14rJf0rRatmywTtt8h7QjfBgJIY6aB_F4h16K2AIyFV1omuUMo2wNj3WoscMFjoCRv6oXwo-R0ZtVTXItEc6EaxD14Wi7Tn9LlaS2rWihtXV6keafYdPCv8ReZ4h8uegJBbIgeo5yGFeWxz2VY_6GeqxFZ59TROoE9CojttmxzzFzmqVA2oNKLla5eLpkzmDCrzNmtUsNXgQOga-dPp6qfHH7P7rbMHZ5HqxkKUGRahRfWafU7uJ1mQBs89VMH8vH2a3Em1SQOlSlS8WgtQ45VUVJVAtlyeN8ccQwGF_QP1OBJ7JBtGLgyyoGSQV0-WIRHP15hHq1rlyffr5Hzpd3uMY9Q1wN0XuSKWGo5qbRDkRu33xMunClEjxYLmcYf3vPGA_wM5NwOpkfY9Xfvu84_sAYkFhKhVmTCaE4oXhhePFxIuFFxsvDl5cvHhw-VU83CjZkRWcOKmpQv3q76_6cQvFbfkzH1_CCx563PO_FFERiwuY02uLXh__5kj5kySQVz_AwZdDFl8Mn5dblmeyL08X4Wbtr93AZla4CUTA2ToMndDwgsBz3UA4X2J_LeIcJYKow2m7SHBhBfkdP47KvXYmp_X4aF1_iS5gpGKGbbgU3yawJx7UHQb1DHvtCzcMbJicCsjg8QS5m6TZ9kt2IRldH7Y5fImFWl5_CeMyzCuFVCvi9w_FU5pd3P-xjCBVf5EyXUiB_gvDSTd-">