<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/55612>55612</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [AMDGPU][MC][GFX940] v_mac_f32_dpp should be disabled
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            bug,
            backend:AMDGPU,
            mc
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
            dpreobra
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          dpreobra
      </td>
    </tr>
</table>

<pre>
    v_mac_f32 is not a valid GFX940 opcode. However the following dpp variant of this instruction is accepted by llvm assembler:

    v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf

Assembler trigger errors for other variants of this instruction but these error messages are misleading; they suggest that the instruction is supported. For example:

    v_mac_f32 v5, v1, v2
    error: operands are not valid for this GPU or mode

The root cause of this issue is that the opcode is only supported on GPUs which have HasMadMacF32Insts feature. But the feature is defined using OtherPredicates that are not propagated from pseudo to real instructions.

A fix is pending.
</pre>
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