<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/55615>55615</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [RISCV] Selection of VL for splat constants causing vsetvli toggles
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            backend:RISC-V,
            llvm:codegen,
            performance
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          preames
      </td>
    </tr>
</table>

<pre>
    I noticed that we unconditionally treating splat constants as effecting all lanes in a vector register.  

Example:
```
define void @vector_splat_toggle(double* %a, double* %b) {
entry:
  %addr = bitcast double* %a to <vscale x 1 x double>*
  tail call void @llvm.riscv.vse.nxv1f64.i64(<vscale x 1 x double> zeroinitializer, <vscale x 1 x double>* %addr, i64 4)
  %addr2 = bitcast double* %b to <vscale x 1 x double>*
  tail call void @llvm.riscv.vse.nxv1f64.i64(<vscale x 1 x double> zeroinitializer, <vscale x 1 x double>* %addr2, i64 4)
  ret void
}

; Function Attrs: nounwind writeonly
declare void @llvm.riscv.vse.nxv1f64.i64(<vscale x 1 x double>, <vscale x 1 x double>* nocapture, i64)
```
Repro command:
`$ ./llc -march=riscv64 -mattr=+v < debug-splat.ll `

Key output:
```
        vsetvli a2, zero, e64, m1, ta, mu
        vmv.v.i v8, 0
        vsetivli        zero, 4, e64, m1, ta, mu
        vse64.v v8, (a0)
        vse64.v v8, (a1)

```
As you can see here, we setup VL to be VLMAX for the splat, despite the fact we only use four lanes of the resulting value.  We could have used AVL=4 the whole way through on this example.

This example is written with scalable vectors, but this also shows up in idiomatic fixed length vector loops.  As an example, see  `@vector_init_vsetvli_fv` from `test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll`.  
</pre>
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