<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/55494>55494</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            Decoding conflict with addressing mode 'r' and 'd'
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            backend:m68k
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          0x59616e
      </td>
    </tr>
</table>

<pre>
    ## Problem
Addressing mode 'r' has encoding '????', and addressing mode 'd' has encoding '0???'. These two are ambiguous. Disassembler can't decide whether, say for example, '0001' ,belongs to which addressing mode.

## Affected instructions
OR16dd / OR16dr
OR32dd / OR32dr
SUB16dd / SUB16dr
SUB32dd / SUB32dr
AND16dd / AND16dr
AND32dd / AND32dr
ADD16dd / ADD16dr
ADD32dd / ADD32dr

## How to reproduce
```
$ cd <llvm-project-root-dir>/llvm/lib/Target/M68k
$ <llvm-project-binary-director>/llvm-tblgen -I ../../../include M68k.td --gen-disassembler 1>/dev/null
...
Decoding Conflict:
                ................................................................1000...00100....
                ................................................................1000............
                ................................................................................
        OR16dd 1000___00100____
        OR16dr 1000___00100____
Decoding Conflict:
                ................................................................1000...01000....
                ................................................................1000............
                ................................................................................
        OR32dd 1000___01000____
        OR32dr 1000___01000____
Decoding Conflict:
                ................................................................1001...00100....
                ................................................................1001............
                ................................................................................
        SUB16dd 1001___00100____
        SUB16dr 1001___00100____
Decoding Conflict:
                ................................................................1001...01000....
                ................................................................1001............
                ................................................................................
        SUB32dd 1001___01000____
        SUB32dr 1001___01000____
Decoding Conflict:
                ................................................................1100...00100....
                ................................................................1100............
                ................................................................................
        AND16dd 1100___00100____
        AND16dr 1100___00100____
Decoding Conflict:
                ................................................................1100...01000....
                ................................................................1100............
                ................................................................................
        AND32dd 1100___01000____
        AND32dr 1100___01000____
Decoding Conflict:
                ................................................................1101...00100....
                ................................................................1101............
                ................................................................................
        ADD16dd 1101___00100____
        ADD16dr 1101___00100____
Decoding Conflict:
                ................................................................1101...01000....
                ................................................................1101............
                ................................................................................
        ADD32dd 1101___01000____
        ADD32dr 1101___01000____
```

##  Miscellaneous

In addition to the instructions above, there are conflicts with tail call instructions. I haven't  looked into it, and I'm not quite sure whether it's critical for us.
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJzdWEtzpDYQ_jXMRTUUEgz2HDh4TVzxYZNUsnt2CdQDigVyJGGv_31avAbPenxJGbtCARLqp9Rqmo9Ci-csYDGe5A-jCwVNEOVBdHUlhAFrZVuRRgsgAbsweJGaWwJtqYWn4EAQ3xxPfGTXhLeC8J_FxWvi0VI4JN9qsEDckybcAOFNIatOdzYkubTcWmjQQUNK3iK3IwJKibqfanA1GG_a8mdy0IbAD948KPBD3kgUUW8cHwtQuq0scRrFZFmfOhoOsx_vw7pcHQ5QOhBEttaZrnRSt3bg-P1PmgqBim9I3zXTcMzmYeyOw399_zKzD_0jYRYY-iPh6rd8lhj6R8IsMfQnQr6QyJcS-UIiX0i8mOuv-smvjYEHo0VXwkhMo_EceRNSoqb4WqnHZousf-MCbY3WbiukCeJf0Ign-UYWeP_GTQUOO1_Ty_ujklMNhWy5efY68EkvFG1doSpoyfaWhCGOHW-yLVWHm8ArDp0g2y3yoYbFdqGDHgGPeG87pQYHwnAMdg7jfrzW7UHJ0gXxuCjk5Aj_40FxJ2KD27Fvw3e1Mh_vY-X0eGllTAzvyt3dXT9hbO9eYTJnmNaPyrRu_-eo9K-AacHH9qeo-HfDGaZVo0LDNXKFLp8_IipTWfC-nE-WsWCc4Vo_Lu-eLZ8hLlO60PPpMtbrM1wrxoWuUlvox7_Fpo8iSt8qLuPn0hmu9ePyzvnyOeIy5At9q7yMX6tnuFaNyxr1hX78e2yCBN6XN_Iln_PlY-sLXaW-fI64TPnyRn0ZsdoZrlNktsRy5Ku0JSjFW0AMvWS4bT3ulR7IerSH6PkFtiW80I89ePa4GnosXo5xt-RJupo4LhXicKVeCIbkFhH-IwzwnCit73vYjDakm34N3CKxIa125J9OOiC2MzOG79kuLCkNOofqezCP-H8jsljs4z3fOOkUZPN2nNwavHrlr0P_08KbHf9AbDqjstq5B-t3MLvBs0LRrghL3Sxg6wKWepRpbQcWO7tdsk82dRal7JLFIokPHIfi5DKBOC1oEjG4FPFuv1G8AGWzYPclYKzg5T20Ai02Hv8yFuzyjcxYxFi0o2kUR0kShynjXDB2QeOYccrjIImgwXUOvTOhNtXGZL1fRVdZJCppnT0SEfDKqgXobaJ-3rlamyz6sdunNIVNP4esn8C_Ibgcpw">