<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/55296>55296</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            fshl-related miscompile by arm64 and x86-64 backends
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            backend:AArch64,
            backend:X86,
            llvm:codegen,
            miscompilation
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          regehr
      </td>
    </tr>
</table>

<pre>
    ok this one is a bit of a pain so please bear with me:

```llvm
declare i7 @llvm.fshl.i7(i7, i7, i7) #0

define i7 @f(i7 %0, i7 %1, i6 %2) {
  %4 = sext i6 %2 to i7
  %5 = call i7 @llvm.fshl.i7(i7 %0, i7 %1, i7 %4)
  ret i7 %5
}
```
let's play through what this code should do when called as `f(8, 0, 39)`

`%0 = 0b0001000`
`%1 = 0b0000000`
`%2 = 0b100111`
`%4 = 0b1100111`

the concatenation of `%0` and `%1` is `0b00010000000000` and the shift amount is 103 mod 7, or 5. thus, after the shift we get a run of all zeroes, therefore `f(8, 0, 39)` should be `0`.

Alive2 agrees with this analysis: https://alive2.llvm.org/ce/z/Ph-9vE

but this isn't what we get from either the x64 or arm64 backend. let's use this driver:
```
#include <stdio.h>

// define i7 @f(i7 %0, i7 %1, i6 %2) {
unsigned f(unsigned, unsigned, unsigned);

int main(void) {
  printf("%u\n", f(8, 0, 39));
  return 0;
}
```

on x64 we get:
```console
regehr@john-home:~$ llc foo.ll && clang foo.c foo.s && ./a.out
8
regehr@john-home:~$ 
```

and on arm64:
```console
Johns-MacBook-Pro:~ regehr$ ~/llvm-project/for-alive/bin/llc foo.ll && clang foo.c foo.s && ./a.out 
8
Johns-MacBook-Pro:~ regehr$
```

cc @ornata @nunoplopes @ryan-berger @nbushehri @zhengyang92 @aqjune @Hatsunespica
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJylVVtvqzgQ_jXkZRTEJZDwwEPanuhopZXO474aMODWsXN8aZv--p0xpLm0PZV2JTBjz338zdDo7ljrJ3CjsKAVB_wwaIQD3SNxYEKB1XCQnFkODWcGXoQbYc-jfBslD1FyWstkeqR83k9HHW8lM2hyDdEqnMe9HWUs1lG2oeUezmsFUZYnlxY73gt10u6DCsoUyaRBZBrIksgsWFjfTapARyuI8gew_NWdZMBp8nUWKYJIy6T8KshPPQZyhR5Ppgx382kxZ7B-uCnLtJXcRdnaYj3ZEWtutB9GeBmZmy6g1R0HO2ovO-g0MrgK0fEOmAW0QmXYUAwhpryiGMrk9h4w5JBY0iRJkuJ7lgnc9MxNPnKzmYuKaZreMFcn5i03rG7kmINqmeOKOaEVoWiOCD_AVDdvSZOwhp_3KM_hBEEyZkfRO2B77ZUj8TTJYa87CLDRBooYxbylHesdNxdKLxwGvBYGxocw6JLfuNE8SKOc4b1GdH5Z1dNFNEGGwoovc91K8cwzYIPh3E5NEe6QKSaPVljsDxidOxARZTt8WNCIA8a0GfCk5bi84ftrXFbPPy7NN37GhLAKIeMmlMxJ9UbvgQtKImT8Wq6oGszskWhY-8RVF8MJbB47N5jqDAZgzo17jU3sP6Fa6RGCUX5vXSd0PEb5VVRTIvA_WtMrKwaFgCa104aEP6erKL-7DEAgDvY4lFD5WYvupusPBvlkOMrQa-Gj4l4F8h4-u-ML66GHvVHIfnf4RQ9PK2Kbqj5dyMeSYhdYLfl0avjAR4OletSjWo56Gp7rH1G2Ailb6LVGVGCtSnwAh6YawtnEsSdGTBiKtXeT1c33xv8QP3UY5hAg8034f6Fhu_ybtXdaPy1_GT05gNkz-SF3OwL28mD0I28ReDvsrmWAPNIN3djuv-QKV8l-G8ofMm5bQqs2OJkYUcorfZD6gN2LO3NkatlwM2BLEbPxdkSTgjZvOIcH5A9VRlv2-9Ej-pH6yZxF0h5EyxZdnXdVXrGFE07ymv4iS8MlzsIO9sK2en8QEv-hx7lP6QZeN-Xy3LJ24Y2sr4fGgF3umxi15wp_LLSw1tNU2xVFVpWLsS7zJK_Wad9sKrRcrtJ8neLoTjZV3iY9qxaSNVzaOirusDtm5-hxuzXtiHCYOuaK9c-mPB-HMPIt_a0Grs7n71mG2U_nxcNC1FmSZUmRlEmaZ2kZZ-Wm4lWaZSxNm4JXWEeOLS3fB-PC1CHDxg-W_snCOntmMhtmAw_Ro33m3ahNPSFgEWpRh0L8C_-le8A">