<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/55271>55271</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            arm64, x86, and x86-64 miscompile from undef and urem
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            backend:AArch64,
            backend:X86,
            llvm:codegen,
            miscompilation
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          regehr
      </td>
    </tr>
</table>

<pre>
    ```llvm
declare i32 @llvm.umax.i32(i32, i32)

define i32 @umax(i32 %in) {
  %x = call i32 @llvm.umax.i32(i32 undef, i32 undef)
  %y = urem i32 %x, 3
  ret i32 %y
}
```
the x86, x86-64, and arm64 backends turn this into a bare `ret`, allowing it to return any i32 value, but it's clear that the `urem` cannot produce all values

this feels similar to #55178 but is not fixed by the candidate patch for that issue, so reporting separately.

cc @ornata @nunoplopes @ryan-berger @nbushehri @zhengyang92 @aqjune @hatsunespica
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJx9U8mSnDAM_Rq4uKYLzNYcOPSka74hVwFq8MTYxMukyddHNjCZXFJFYa1PT5Ld63HrkjrbPyk_liS7J9ltxEGCQSYKzpIyOi5-geeFDAm_xv83Fo92zzjzHkJ9poWMPZolvBKKglnSvO6hLNieLCnubAAp_1OKeUW4R8FTab-gbBHFG1zYUesZooszxKA7HdvBtrkfwtn7rroZ2fNah2w6XuoySKBGBmapS9bD8APVaJnzRjE3C8uEcpoBeWhaBEOlAljIklL_EmpiwjEKIUfIAbVFKh8gPYaw3hM3l_DGskEiGEIFSpgjWmiJDhqQUtqx1ejRDxigdwD7dfaRzgNRWmbFImTA0tRzUVV5c90LWRZwHuKJI-u3WIawRzGCQ7aCG2b20AcHYe1O0Qb2qzYudGNxBUPRcrt8LT4MYXnaKHAQJOWVXqVe0QbNbKBeejQTmujsvZ1xNiIov2dUE_mnNu4ffr57ukEkEQdLol3FAOnYFWNbtJA64SR2cR3Hls4V7Qtji7CDXlYhkT2MXvb7EgPCNFNvZDc7t9qkuCX8jb5JuNn3F0oiJT6B_Xihcb_jQLt5i6OwJFQVb_J07vK2bK75APAoENo259m1zMY2f_A6K-prlUroaRFdUr0mnB_XhirebmaYA_P4fv5xfQ-dnOZIo7gNesQJ1V_7Z3PghI726p6KjmecZ1VW5hUvcn7py6Zpx75oWiRzXdEwcQEhL_FxaTOlposd9n6y4c0J6-xfJ1grJoUY2RM-eDdr0xmiMps0zqKLg_gDuPxKhw">