<table border="1" cellspacing="0" cellpadding="8">
<tr>
<th>Issue</th>
<td>
<a href=https://github.com/llvm/llvm-project/issues/55212>55212</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>
[RegCoalescer] Liventervals updating fails
</td>
</tr>
<tr>
<th>Labels</th>
<td>
llvm:optimizations
</td>
</tr>
<tr>
<th>Assignees</th>
<td>
arcbbb,
rampitec
</td>
</tr>
<tr>
<th>Reporter</th>
<td>
JonPsson
</td>
</tr>
</table>
<pre>
[testcase.tar.gz](https://github.com/llvm/llvm-project/files/8599095/testcase.tar.gz)
llc -mcpu=arch13 -O3 -disable-machine-dce -verify-machineinstrs tc_crash0_aftercreduce.ll
```
# After Simple Register Coalescing
********** INTERVALS **********
%0 [320r,320d:0) 0@320r weight:0.000000e+00
%1 [176r,224d:0) 0@176r weight:0.000000e+00
%3 [96r,176r:0) 0@96r weight:0.000000e+00
%12 [16r,32r:0) 0@16r weight:0.000000e+00
RegMasks:
********** MACHINEINSTRS **********
# Machine code for function e: NoPHIs, TracksLiveness, TiedOpsRewritten
0B bb.0.bb:
successors: %bb.2(0x80000000), %bb.1(0x00000000); %bb.2(100.00%), %bb.1(0.00%)
16B %12:grx32bit = LHIMux 0
32B CHIMux %12:grx32bit, 0, implicit-def $cc
48B BRC 14, 6, %bb.2, implicit killed $cc
64B J %bb.1
80B bb.1.bb2:
; predecessors: %bb.0
96B %3:gr64bit = LGRL @b :: (dereferenceable load (s64) from @b)
176B %1:gr64bit = SRLG %3:gr64bit, $noreg, 24
320B dead %0:gr64bit = LGHI 0
336B bb.2.bb4:
; predecessors: %bb.0
352B Return
# End machine code for function e.
*** Bad machine code: Live segment doesn't end at a valid instruction ***
- function: e
- basic block: %bb.1 bb2 (0x2aa1e9bf140) [80B;336B)
- liverange: [176r,224d:0) 0@176r
- v. register: %1
- segment: [176r,224d:0)
LLVM ERROR: Found 1 machine code errors.
```
</pre>
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