<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/55199>55199</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            AArch64: 128b LSE atomic instructions not generated
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          sebpop
      </td>
    </tr>
</table>

<pre>
    Testcase https://github.com/llvm/llvm-project/blob/main/llvm/test/CodeGen/AArch64/arm64-atomic-128.ll compiled with -mattr=+lse shows that several cases are not generating LSE instructions.
For fetch_and_max https://github.com/llvm/llvm-project/blob/main/llvm/test/CodeGen/AArch64/arm64-atomic-128.ll#L347 LLVM generates armv8 ld/st exclusives `ldaxp`/`stlxp` which are an order of magnitude slower than LSE instructions on Graviton processors Neoverse-N1:
```
    ldaxp    x9, x8, [x0]
    cmp    x9, x2
    cset    w10, hi
    cmp    x8, x3
    cset    w11, gt
    csel    w10, w10, w11, eq
    cmp    w10, #0
    csel    x10, x8, x3, ne
    csel    x11, x9, x2, ne
    stlxp    w12, x11, x10, [x0]
```
This bug impacts performance of Rust programs for which LLVM generates code without LSE instructions.

</pre>
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