<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/55041>55041</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            AArch64: SVE: LLVM ERROR: Error while trying to spill X22 from class GPR64: Cannot scavenge register without an emergency spill slot!
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          rscottmanley
      </td>
    </tr>
</table>

<pre>
    llc is getting abort in the Register Scavenger when using -aarch64-sve-vector-bits-min=256 and the -mcpu=neoverse-v1 target. It seems to be okay on a64fx and -aarch64-sve-vector-bits-min=512.

bugpoint reduced testcase here: https://godbolt.org/z/Er19PW8M1

cc @mcinally @paulwalker-arm 
</pre>
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