<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/54866>54866</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            Bad machine code: Missing mayLoad flag (reg coalescer DCE)
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            llvm:codegen
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          JonPsson
      </td>
    </tr>
</table>

<pre>
    [testcase.tar.gz](https://github.com/llvm/llvm-project/files/8471333/testcase.tar.gz)
Original test case:
clang -O3 -march=arch13 crash0.i -o a.out -w -fno-inline -mllvm -disable-lftr -mllvm -disable-machine-dce -mllvm -enable-tbaa=false -mllvm -verify-misched

Reduced test case:
llc -mcpu=arch13 -O3 -disable-lftr -disable-machine-dce   tc_crash0_aftercreduce.ll -verify-misched

It looks like Simple Register Coalescing is performing some DCE which removes an LOCMux (Load On Condition) by turning it into a KILL:

160B      %0:gr32bit = LOCMux %0:gr32bit(tied-def 0), %5:addr64bit, 0, 14, 6, implicit killed $cc :: (dereferenceable load (s32) from @c)
176B      CHIMux %3:grx32bit, 0, implicit-def $cc
=>
160B      KILL implicit killed $cc :: (dereferenceable load (s32) from @c)
176B      CHIMux %3:grx32bit, 0, implicit-def $cc

The MachineVerifier then later complains, and it seems like it is expecting any instruction with a memory operand to have the mayLoad flag...

</pre>
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