<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/54811>54811</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            Wrong Resource Usage for BSR and BSF Instructions in Znver1 Scheduling Model
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          fabian-r
      </td>
    </tr>
</table>

<pre>
    When given one of the following 1-instruction basic blocks, llvm-mca reports an Rthroughput of 0.3:
```
bsr %rbx, %rdx
```
and
```
bsf %rbx, %rdx
```

Measurements with nanoBench and uops.info, as well as AMD's Latency Table, say that they are slower:
- BSR has a throughput of 0.25, i.e. an Rthroughput of 4
- BSF has a throughput of 0.5, i.e. an Rthroughput of 2 (according to AMD's table; I did not observe anything lower than 3 with nanoBench experiments)

The problem seems to be that the corresponding [entries in the scheduling model](https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/X86/X86ScheduleZnver1.td#L234) only use a single ZnALU resource although the instructions use 6 uops.

According to uops.info data, znver2 is affected as well.

</pre>
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