<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/54690>54690</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [AMDGPU][MC] Assembler fails to detect unsupported 64bit DPP opcodes
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            bug,
            backend:AMDGPU,
            mc
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
            dpreobra
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          dpreobra
      </td>
    </tr>
</table>

<pre>
    64-bit DPP opcodes are supported on GFX90A and GFX940 only. However assembler fails to identify these opcodes as unsupported when they are used on other GPUs. 

An example of failed test (GFX10):

    v_ceil_f64_dpp v[10:11], v[2:3] row_newbcast:1 row_mask:0xf bank_mask:0xf

Expected output:

    error: dpp variant of this instruction is not supported

Actual result:

    error: not a valid operand

The reason for this bug is contamination of matcher tables with disabled opcodes:

    static const MatchEntry MatchTable4[] = {
      ...
      { 15152 /* v_ceil_f64 */, AMDGPU::V_CEIL_F64_dpp8_gfx10, ..., AMFBS_isGFX10Plus_HasDPP8, ...
      ...
      { 15152 /* v_ceil_f64 */, AMDGPU::V_CEIL_F64_dpp_gfx10, ..., AMFBS_isGFX10Plus_HasDPP16, ...

A fix is pending.

</pre>
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