<table border="1" cellspacing="0" cellpadding="8">
<tr>
<th>Issue</th>
<td>
<a href=https://github.com/llvm/llvm-project/issues/54611>54611</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>
DWARF location info not aware of instruction scheduling updates
</td>
</tr>
<tr>
<th>Labels</th>
<td>
new issue
</td>
</tr>
<tr>
<th>Assignees</th>
<td>
</td>
</tr>
<tr>
<th>Reporter</th>
<td>
cristianassaiante
</td>
</tr>
</table>
<pre>
In this minimized C example, variable l_73 used in the first assignment of variable f at line 8, is not available during debugging although it is alive and initialized to constant 0.
This behavior appears to be caused by the Machine Instruction Scheduler on function (main) pass that re-schedules the instruction associated with line 8 and updates the DWARF location info in a way that does not include the involved line anymore.
```
$ cat a.c
int a, d;
char b;
volatile char c;
int main() {
{
int e = b;
char f, l_73 = 0;
f = l_73 < c;
d = e == 0 ? 0 : a % e;
}
}
```
LLVM version:
```
$ clang -v
clang version 13.0.0
Target: x86_64-unknown-linux-gnu
Thread model: posix
InstalledDir: /usr/local/bin
Found candidate GCC installation: /usr/lib/gcc/x86_64-linux-gnu/7
Found candidate GCC installation: /usr/lib/gcc/x86_64-linux-gnu/7.5.0
Found candidate GCC installation: /usr/lib/gcc/x86_64-linux-gnu/8
Selected GCC installation: /usr/lib/gcc/x86_64-linux-gnu/7.5.0
Candidate multilib: .;@m64
Selected multilib: .;@m64
$ lldb -v
lldb version 13.0.0
```
LLDB trace:
```
$ lldb opt
(lldb) target create "opt"
Current executable set to '/home/stepping/962/reduce/opt' (x86_64).
(lldb) b 8
Breakpoint 1: where = opt`main + 7 at a.c:8:16, address = 0x0000000000400487
(lldb) r
Process 402 launched: '/home/stepping/962/reduce/opt' (x86_64)
Process 402 stopped
* thread #1, name = 'opt', stop reason = breakpoint 1.1
frame #0: 0x0000000000400487 opt`main at a.c:8:16
5 {
6 int e = b;
7 char f, l_73 = 0;
-> 8 f = l_73 < c;
9 d = e == 0 ? 0 : a % e;
10 }
11 }
(lldb) frame var
(char) l_73 = <variable not available>
(int) e = <variable not available>
(char) f = <no location, value may have been optimized out>
```
ASM of main function:
```
0000000000400480 <main>:
400480: 0f be 0d a5 0b 20 00 movsbl 0x200ba5(%rip),%ecx # 60102c <b>
400487: 8a 05 a0 0b 20 00 mov 0x200ba0(%rip),%al # 60102d <c>
40048d: 85 c9 test %ecx,%ecx
40048f: 74 0b je 40049c <main+0x1c>
400491: 8b 05 99 0b 20 00 mov 0x200b99(%rip),%eax # 601030 <a>
400497: 99 cltd
400498: f7 f9 idiv %ecx
40049a: eb 02 jmp 40049e <main+0x1e>
40049c: 31 d2 xor %edx,%edx
40049e: 89 15 90 0b 20 00 mov %edx,0x200b90(%rip) # 601034 <d>
4004a4: 31 c0 xor %eax,%eax
4004a6: c3 retq
4004a7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1)
4004ae: 00 00
```
DWARF info:
```
0x000000b7: DW_TAG_variable
DW_AT_location (0x00000000:
[0x000000000040048f, 0x00000000004004a7): DW_OP_consts +0, DW_OP_stack_value)
DW_AT_name ("l_73")
DW_AT_decl_file ("/home/stepping/mismatches/llvm-mismatches/dd-mismatches/962/reduce/a.c")
DW_AT_decl_line (7)
DW_AT_type (0x00000070 "char")
```
We can see how the location definition of variable l_73 does not include the instruction at address 0x400487 which is associated with line 8 in the line number table.
With opt-bisect-limit we found out that the optimization pass that introduces the issue is Machine Instruction Schedule.
ASM of main function before Machine Instruction Scheduler:
```
0000000000400480 <main>:
400480: 0f be 0d a5 0b 20 00 movsbl 0x200ba5(%rip),%ecx # 60102c <b>
400487: 85 c9 test %ecx,%ecx
400489: 8a 05 9e 0b 20 00 mov 0x200b9e(%rip),%al # 60102d <c>
40048f: 75 04 jne 400495 <main+0x15>
400491: 31 d2 xor %edx,%edx
400493: eb 09 jmp 40049e <main+0x1e>
400495: 8b 05 95 0b 20 00 mov 0x200b95(%rip),%eax # 601030 <a>
40049b: 99 cltd
40049c: f7 f9 idiv %ecx
40049e: 89 15 90 0b 20 00 mov %edx,0x200b90(%rip) # 601034 <d>
4004a4: 31 c0 xor %eax,%eax
4004a6: c3 retq
4004a7: 66 0f 1f 84 00 00 00 nopw 0x0(%rax,%rax,1)
4004ae: 00 00
```
DWARF info before Machine Instruction Scheduler:
```
0x000000b7: DW_TAG_variable
DW_AT_location (0x00000000:
[0x0000000000400489, 0x00000000004004a7): DW_OP_consts +0, DW_OP_stack_value)
DW_AT_name ("l_73")
DW_AT_decl_file ("/home/stepping/mismatches/llvm-mismatches/dd-mismatches/962/reduce/a.c")
DW_AT_decl_line (7)
DW_AT_type (0x00000070 "char")
```
By diffing the ASM we can see how the pass is responsible for relocating the instruction `mov 0x200b9e(%rip),%al` which is the one associated with line 8 in the line number table.
We can see how before instruction scheduling, the location definition of variable l_73 includes the instruction at 0x400489 that is associated with line 8.
Attached to this report you can also find the IR before and after Machine Instruction Scheduling.
[pre.ll.txt](https://github.com/llvm/llvm-project/files/8370020/pre.ll.txt)
[post.ll.txt](https://github.com/llvm/llvm-project/files/8370023/post.ll.txt)
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJztWd2Po7YW_2syL9ZEBgKEhzzMJJ1qpa5u1V11H0fGmMS7gLnGJJn-9T3HfCdkdne696qVimYI2D6fPj7nZxOr5GXzriDmICuSy0Lm8g-RkC0RZ5aXmVi4W3JkWrI4EyR7Dj1SV9AvkUKQVOrKEFZVcl_kojBEpcPolDBDMlkIskYuwL9QMPjIZGb7k1rLYk8SEdf7PT6xzBxUvT8QaXA0y-RREFagNGkkvKJmRhGuisowkEaXZEF3C_rQ3D-iDbE4sKNUmrCyFExXSBALwpnVO36xer9n_ICKvQNGuuZGqoJ84AeR1JnQBF7SumhaF-46Z7JYuBEpwU6gBqO0uK_a0ZXlJ0d8YJTikhmQdpLm0HrA2lGXCbQ3JLtPD789kUxxZqlkkSr0KiMn9tJISZRoXCYLntWJaCUdVXYE3pYtK15ypcVy7IVFQNu_5tVdgfHg9yVvGiQ4juGEJAvvsWniB6ZJ3L-CBFAKZsi2874dKRtnrNEfi7BtHz0RgoMEWXi7EUNotqxSFGuDCPvpuD-1TW3fdiQU-hLbZ5laOnh4svcHcNfC9YkYRi_CXWt3_3DhD3v_5Zff35Oj0BX4Hvjc9lzGIDDvj62f7FtLRhxvSZft2I9M74VBjc7r4DlY3dfFl0KdinuYpvp8vy_qLkS1YAnJVSIyHF2qSp6bLoxFlmUi2UmNXQv3qa403DFGMviNwfN25JOqIZg4RJTEeCI_b7c2AoHaBtOUWsZw33MO91a3QSf3KfwfsFz6nVt-JNt1w_KDyATHxfWDVNz2yuV1BlEPhMBoiRG1onmwupD62qAhbLIsifuosS9zQXMjMnePxGjGxWtxaXmq0nQta2zARWlsIBIOYQYmLVwXB7lua2utNWZpcRa8NjYJVzAYMuTCDcEtB5VDwn-qjChLSMjwGAUu3DWkOo49llmISbFxKkhcXqkQk3aqHkGJL6XCjOCgv04HoZvUgHwCirkEeD2SkLQJyntYw78TYJ5gSaIFZFy75M-0v1bwtw6vpGqCV9P8q1YcSVfUJRmDVA65ugmPt1p5zbcyCgpM0unxANnZLu2F6zmofsHyxlZg1TDEVqSC8sEqLC2YI0cuWjp9xiOptuSuR1Hva_PHHrz0XcfEJ41LRsk5IO11I0uHXf-r6fp-4f0EFa29XsvcUTfoe1I4IQ5tNd8NTc64YTTvjacAdPQ9qDv29JqDWj0omUAQsGO6ctfgFyQV30vXyUw7wkL1tb2BUFkNGQZKO6ATAYBEFDiFLdpStRlYziWFhw_vEVrZ6e6gya30cBEq6OStrdogoSMhTRe6v7loiiCJJoT5hMbEpYTaOcjVsYozCECX0pj5tvL7Wpa4JNwtPAt-7uYYopUE1KEuR5FxbxFpV2wvbM0I9QmjE0mNMKtLI4xeC2PZlSwMrC2_kJWMZPmE91E4ugCGGcsHLehNGTNJBybhClW9vj4L-4PDI9772X2kZ-dCpcgZqRSj-VH0qvlRNONrduVrz04vuxA28nU0ZzxcPDOJZTQiWw9kaUjSOUqZyOPgthEtG2gF2OfOeSsve2-JqbfEhQF84OY5JJnjdlaatJok3QQmE5XEyOURccDltyKuZ9L6fhJ6Vy5foe7JVGO2mmjMKbm-Rhqzcz-jYybBwIR7Mxzg0sL813IZkY2mOwhwKTspWa_QStrZWqjyRDC2OtM6DZoHpy9xDceR6yyLDlzP5aZmI4P7l5sZqS1f8UjR3afnjw8_P3f5dah8lxcMfPj43O-T2qlYDyXRFvab5Djaf7wqoLa0XbaCI8ENwA5k_ufXZ7vNrBCgUBzdNALe5F-ebToffHZTbQsCiHW5i-UIkdjXqRLBs-cUN2CtsZZsBrfkssqZAXRTIeTNjvn9pCVJpu8XMAdBw7frY_ebrT7hNxCZl1JMZiqkCEebQjlInQ2pT7hfLwCbCnJQJ7vv7QMgEak9DoDH8WGDLfY3dsyjvbnpYSU9t0jqdJD8YM8b5jfu7VGHfSvqPBaaWOg82XR_QgIo6PexrGCjAJuNXBpyEiS1OyAo8M2eHjm1db8xZzhUAOihFU5Ne6RQVTXeXz2rmOgwBxKgqqdKf-XA4x-MJN5c3aNLOAIl6dV6LN4OR8ZIApyymlH4c7O4bN3yp7XRv40k3l4bvWm5nvPhd5Rr_wrc-K87c276vxXcxG8DN_wvgJt_kcT_GUn8tbT194Mb0b9w428MNx5fSCLTFD9BYOXFOnq6RiC2UkM9BvRQwlRJ-4kDFqIWTbS01GO4gSc0Xy8iMGoAIRYg4Mn-m8DIBXBqV9FYpfa7hZ3Q7bcjqxZQzXztMB2SiloYcwtITbGKgcA-NJ9z7KcnLUqlDXlRtbWAZZUioE5iBb77rTMFv6Kw1IDZr6QGMG76RcR_LLVYZtnSnM3C38EkHIwpK0wg7hOeE4OWdbzkKm8Du4vvUqvPAOfgFdcHBvXaCyl1YYU-jVj20QWCVGV-pCQPJY149qLs_S7ZeEnkRezOSJOJzdxHJXtydWLgPJjV-VDoP0zd1TrbfLfGFqqiyv4qcJy7wyaJfJe6MGVBwCldQ9wDagvXAfRTTll0l7FYZNUG_AWLsxCnBu3iQvV3d3IDxC713IhGnuMHS-4EqRMmNPDWPAxDsVhRAWAkW6IeS6X3d3pjVYrrfQWdmYREOnQ2nyeFsOKAP6vNQekN1zBMsgK6GfwYcWeV2Fgj_gSQG9Tz">