<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/54459>54459</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            IR Outliner: Assertion failed: (VT.isInteger() && Operand.getValueType().isInteger() && "Invalid TRUNCATE!")
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            llvm:crash,
            llvm:optimizations
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          ornata
      </td>
    </tr>
</table>

<pre>
    Sometimes the IR outliner creates outlined functions which SelectionDAG can't handle. This also crashes GlobalISel but differently. It could be a selector bug, but it's more likely an IR outliner bug.

### Reproducing the issue

Compile the attached LLVM IR using a debug build of clang:
 
**IR:** [crash.txt](https://github.com/llvm/llvm-project/files/8309899/crash.txt)
**Compiler explorer (which cannot reproduce this, but you can see what's outlined I guess)**: https://godbolt.org/z/e38b8cYhM

```
$ mv crash.txt crash.ll
$ clang -mllvm -ir-outliner -mllvm -ir-outlining-no-cost -O1 -arch arm64 -S -o /dev/null crash.ll
```

You should get

```
Assertion failed: (VT.isInteger() && Operand.getValueType().isInteger() && "Invalid TRUNCATE!"), function getNode, file SelectionDAG.cpp, line 5165
```

### Data dump

Focusing on the SDAG path, since that's where it showed up initially.

Plopping this into LLDB, we can see the issue shows up when selecting an outlined function:

```
(lldb) p Fn.getName()
(llvm::StringRef) $1 = (Data = "outlined_ir_func_1", Length = 18)
```

Ok, so what's inside the function?

```
(lldb) p Fn.dump()
; Function Attrs: minsize mustprogress nofree nounwind optsize
define internal void @outlined_ir_func_1(<9 x float> %0, <1 x float> %1, <3 x float>* %2, <3 x float>* %3, <3 x float>* %4) #2 {
newFuncRoot:
  %5 = shufflevector <9 x float> %0, <9 x float> poison, <3 x i32> <i32 3, i32 4, i32 5>
  %6 = shufflevector <9 x float> %0, <9 x float> poison, <3 x i32> <i32 6, i32 7, i32 8>
  %7 = shufflevector <1 x float> %1, <1 x float> poison, <3 x i32> zeroinitializer
  %8 = fmul contract <3 x float> %5, zeroinitializer
  %9 = fmul contract <3 x float> %6, zeroinitializer
  store <3 x float> %7, <3 x float>* %2, align 16
  store <3 x float> %8, <3 x float>* %3, align 16
  store <3 x float> %9, <3 x float>* %4, align 16
  ret void
}
```

What is the state of the SelectionDAG?

```
(lldb) p DAG.dump()
SelectionDAG has 31 nodes:
  t23: i64,ch = CopyFromReg t0, Register:i64 %8
  t25: i64,ch = CopyFromReg t0, Register:i64 %9
  t27: i64,ch = CopyFromReg t0, Register:i64 %10
    t2: f32,ch = CopyFromReg t0, Register:f32 %0
    t4: f32,ch = CopyFromReg t0, Register:f32 %1
    t6: f32,ch = CopyFromReg t0, Register:f32 %2
    t8: f32,ch = CopyFromReg t0, Register:f32 %3
    t10: f32,ch = CopyFromReg t0, Register:f32 %4
    t12: f32,ch = CopyFromReg t0, Register:f32 %5
    t14: f32,ch = CopyFromReg t0, Register:f32 %6
    t16: f32,ch = CopyFromReg t0, Register:f32 %7
    t19: f32,ch = load<(load (s32) from %fixed-stack.1)> t0, FrameIndex:i64<-1>, undef:i64
  t28: v9f32 = BUILD_VECTOR t2, t4, t6, t8, t10, t12, t14, t16, t19
    t21: v2i32,ch = load<(load (s64) from %fixed-stack.0)> t0, FrameIndex:i64<-2>, undef:i64
  t30: v1i32 = extract_subvector t21, Constant:i64<0>
  t0: ch = EntryToken
```

What is it falling over trying to select?

```
frame #6: 0x000000010613e76a clang`llvm::SelectionDAG::getAnyExtOrTrunc(this=0x000000012cc2b250, Op=SDValue @ 0x00007ff7bfef62f0, DL=0x00007ff7bfef7c18, VT=EVT @ 0x00007ff7bfef62e0) at SelectionDAG.cpp:1361:5
   1358 SDValue SelectionDAG::getAnyExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT) {
   1359   return VT.bitsGT(Op.getValueType()) ?
   1360     getNode(ISD::ANY_EXTEND, DL, VT, Op) :
-> 1361          getNode(ISD::TRUNCATE, DL, VT, Op);
   1362 }
   1363 
   1364 SDValue SelectionDAG::getSExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT) {
(lldb) p Op.dump() 
t30: v1i32 = extract_subvector t21, Constant:i64<0>
```

CC: @AndrewLitteken 
</pre>
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