<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/54359>54359</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            -stress-regalloc triggers assertion
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            regalloc
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
            RKSimon,
            uweigand,
            topperc
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          JonPsson
      </td>
    </tr>
</table>

<pre>
    
[testcase.tar.gz](https://github.com/llvm/llvm-project/files/8237996/testcase.tar.gz)

llc  -O3 -addr-sink-using-gep=false -stress-regalloc=8 -misched=shuffle -o out.s ./tc_regscav.ll
LLVM ERROR: Error while trying to spill R11D from class ADDR64Bit: Cannot scavenge register without an emergency spill slot!

-stress-regalloc=8 limits the number of registers in each register class to 8:
< AllocationOrder(GR64Bit) = [ $r0d $r1d $r2d $r3d $r4d $r5d $r14d $r13d $r12d $r11d $r10d $r9d $r8d $r7d $r6d ]
---
> AllocationOrder(GR64Bit) = [ $r0d $r1d $r2d $r3d $r4d $r5d $r14d $r13d ]

This is changed in RegisterClassInfo.cpp: 'RCI.NumRegs = StressRA'.

This test case is apparently needing register scavenging, and in RegScavenger::scavengeRegisterBackwards() I see that 'AllocationOrder = RC.getRawAllocationOrder(MF)' is used, which includes the full register class, which is a little weird and makes me wonder if -stress-regalloc is broken (it was added 10 years ago by Jakob Stoklund Olesen).

It picks $r11 and then for some reason runs into the assertion above.

</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJy1VMGSozYQ_Rp86YICYRtz4OCxZ1Oz2c2kmK1cU0ISoFhIlCTG5Xx9WoBndndyySFVLrWFWt2vX79WY_ititJzlB6j3YMXzjPqROKpTbq_o905Iofe-9FF-TEin_DXSd9PTcLMgBulXu8mHq35SzCP21Yq4dAeSF6U5R7__RyXlGvKeVWKAcTPOcSUcxs7qS_xhGsXd2KM8nNLlRMQO2-Fc7EVHVXKMDw4QDxIx3rBceP6qW0V-hkwk08cJCEx-xP9HaOviVJLti9f_vgKj3X9XGNN8GitsXDtETJ4e8Ok4A24USoFdZadobVmAKaoc3A8n-v99kH6cPFEtTYeQmihOwGYRjovMBYShACAahCDsJ3Q7LYGdMogP9n3tf9rVUoO0jvwvQA9DQ0GNe1bAgcSI1PWv6dc4CHuQ2jTEj0_wTEEpF4a_Wy5sNjKX1b8pARMBNhxiMjWpnw22WLIYvLFbBezW13WbbaeZqtztt7N1lDlYg6LKRazR4OKWuqO4zvQx_8d6D3psn7rJXLogPUUG8cDnfXK5CkQ-aRbk7BxDF2OSFGfnpLfpgFd3IzlZW5YjeNQJB_CBqFDUHpIQMeRWqG9uoEWggdtvbVs1Q1-i8gJtXKH8bLqyYZO5se7vO4AHyi7XKnlOF6HQM4TOIHC7akPUH_icYZbn5JO-JpeP5L89VMYRFIErJPDIUIkOAmoLKmZmrhYJNhOKN0ftfadJ5aJevUe5-cqpOVzLQO94OUBPxkdgMj2w_iGm401F6ER-UF6uFIMxTk2JEvhJigKnXYGmht8phfTIO_moiYM_oyvi9AI_Qf6nzyMkl3cKscZBqLX0OJ8OzOECaXOaLCTDiOE0xKKw2KEDaQAbcyrWENueJXzMi_pxkusrPoA3lvZdWEW3-5vJquq__xUSuem-a3cbfNduemrHct3BSsEybdsV2RM7MuC8y3ZZU1OtkJsFG2EchVORETI26tBCIp8IyuSEpLmGcmKrEzTpOWNaLYNL9u8afZpG21TMVCpkgAjMbbb2GpG1Eydw0OFPXbvh1ic7FC6a7b61xc5GB2SYf_RTNjxDol-_-LNOAp7x0MnfApt9dno3x1Sv5mrreZS_wFziQ7o">