<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/54202>54202</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            SI Whole Quad Mode causes Bad machine code: Live segment doesn't end at a valid instruction
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            backend:AMDGPU
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          jayfoad
      </td>
    </tr>
</table>

<pre>
    With the attached [test case](https://github.com/llvm/llvm-project/files/8186906/reduced.txt) I get:
```
$ ~/llvm-debug/bin/llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs reduced.txt

# After SI Whole Quad Mode
********** INTERVALS **********
EXEC_LO_HI16 [160r,160d:7)[208r,208d:6)[272r,272d:5)[320r,320d:4)[396r,396d:8)[464r,464d:3)[496r,496d:2)[624r,624d:1)[704r,704d:0) 0@704r 1@624r 2@496r 3@464r 4@320r 5@272r 6@208r 7@160r 8@396r
EXEC_HI_LO16 [160r,160d:7)[208r,208d:6)[272r,272d:5)[320r,320d:4)[396r,396d:8)[464r,464d:3)[496r,496d:2)[624r,624d:1)[704r,704d:0) 0@704r 1@624r 2@496r 3@464r 4@320r 5@272r 6@208r 7@160r 8@396r
EXEC_HI_HI16 [160r,160d:7)[208r,208d:6)[272r,272d:5)[320r,320d:4)[396r,396d:8)[464r,464d:3)[496r,496d:2)[624r,624d:1)[704r,704d:0) 0@704r 1@624r 2@496r 3@464r 4@320r 5@272r 6@208r 7@160r 8@396r
VGPR0_LO16 [0B,16r:0) 0@0B-phi
VGPR0_HI16 [0B,16r:0) 0@0B-phi
%0 [192r,272r:0)[544B,608B:0) 0@192r  weight:0.000000e+00
%2 [304r,432B:0)[608B,624r:0) 0@304r  weight:0.000000e+00
%4 [464r,544B:0)[672B,704r:0) 0@464r  weight:0.000000e+00
%5 [16r,112r:0) 0@16r  weight:0.000000e+00
%34 [112r,176r:0) 0@112r  weight:0.000000e+00
%44 [32r,96B:3)[128r,256B:0)[256B,432B:2)[432B,480r:4)[576r,608B:1)[608B,672B:2) 0@128r 1@576r 2@256B-phi 3@32r 4@432B-phi  weight:0.000000e+00
%46 [160r,192r:0) 0@160r  weight:0.000000e+00
%47 [176r,208r:0) 0@176r  weight:0.000000e+00
%48 [272r,304r:0) 0@272r  weight:0.000000e+00
%49 [480r,496r:0) 0@480r  weight:0.000000e+00
%50 [8r,376r:1)[376r,376d:0)[544B,608B:1) 0@376r 1@8r  weight:0.000000e+00
RegMasks:
********** MACHINEINSTRS **********
# Machine code for function _amdgpu_ps_main: NoPHIs, TracksLiveness, TiedOpsRewritten
Function Live Ins: $vgpr0 in %5

0B      bb.0..entry:
          successors: %bb.1(0x40000000), %bb.5(0x40000000); %bb.1(50.00%), %bb.5(50.00%)
          liveins: $vgpr0
8B        %50:sreg_64 = COPY $exec
16B       %5:vgpr_32 = COPY $vgpr0
32B       %44:sreg_64 = S_MOV_B64 -1
64B       S_CBRANCH_SCC1 %bb.5, implicit undef $scc
80B       S_BRANCH %bb.1

96B     bb.1 (%ir-block.7):
        ; predecessors: %bb.0
          successors: %bb.6(0x40000000), %bb.2(0x40000000); %bb.6(50.00%), %bb.2(50.00%)

112B      %34:sreg_64 = nofpexcept V_CMP_NGT_F32_e64 0, 0, 0, %5:vgpr_32, 0, implicit $mode, implicit $exec
128B      %44:sreg_64 = S_MOV_B64 0
160B      %46:sreg_64 = COPY $exec, implicit-def $exec
176B      %47:sreg_64 = S_AND_B64 %46:sreg_64, %34:sreg_64, implicit-def dead $scc
192B      %0:sreg_64 = S_XOR_B64 %47:sreg_64, %46:sreg_64, implicit-def dead $scc
208B      $exec = S_MOV_B64_term %47:sreg_64
224B      S_CBRANCH_EXECZ %bb.2, implicit $exec
240B      S_BRANCH %bb.6

256B    bb.2.Flow1:
        ; predecessors: %bb.1, %bb.6
          successors: %bb.3(0x40000000), %bb.7(0x40000000); %bb.3(50.00%), %bb.7(50.00%)

272B      %48:sreg_64 = S_OR_SAVEEXEC_B64 %0:sreg_64, implicit-def $exec, implicit-def $scc, implicit $exec
304B      %2:sreg_64 = S_AND_B64 $exec, %48:sreg_64, implicit-def $scc
320B      $exec = S_XOR_B64_term $exec, %2:sreg_64, implicit-def $scc
336B      S_CBRANCH_EXECZ %bb.7, implicit $exec
352B      S_BRANCH %bb.3

368B    bb.3 (%ir-block.16):
        ; predecessors: %bb.2
          successors: %bb.4(0x80000000); %bb.4(100.00%)

376B      dead %50:sreg_64 = S_ANDN2_B64 %50:sreg_64, $exec, implicit-def $scc
380B      SI_EARLY_TERMINATE_SCC0 implicit $exec, implicit $scc
388B      $exec = S_MOV_B64_term 0

400B    bb.4 (%ir-block.16):
        ; predecessors: %bb.3
          successors: %bb.7(0x80000000); %bb.7(100.00%)

416B      S_BRANCH %bb.7

432B    bb.5.Flow:
        ; predecessors: %bb.0, %bb.7
          successors: %bb.8(0x40000000), %bb.9(0x40000000); %bb.8(50.00%), %bb.9(50.00%)

464B      %4:sreg_64 = COPY $exec, implicit-def $exec
480B      %49:sreg_64 = S_AND_B64 %4:sreg_64, %44:sreg_64, implicit-def dead $scc
496B      $exec = S_MOV_B64_term %49:sreg_64
512B      S_CBRANCH_EXECZ %bb.9, implicit $exec
528B      S_BRANCH %bb.8

544B    bb.6 (%ir-block.21):
        ; predecessors: %bb.1
          successors: %bb.2(0x80000000); %bb.2(100.00%)

576B      %44:sreg_64 = COPY $exec
592B      S_BRANCH %bb.2

608B    bb.7.Flow2:
        ; predecessors: %bb.2, %bb.4
          successors: %bb.5(0x80000000); %bb.5(100.00%)

624B      $exec = S_OR_B64 $exec, %2:sreg_64, implicit-def $scc
656B      S_BRANCH %bb.5

672B    bb.8 (%ir-block.22):
        ; predecessors: %bb.5
          successors: %bb.9(0x80000000); %bb.9(100.00%)


688B    bb.9.UnifiedReturnBlock:
        ; predecessors: %bb.5, %bb.8

704B      $exec = S_OR_B64 $exec, %4:sreg_64, implicit-def $scc
720B      S_ENDPGM 0

# End machine code for function _amdgpu_ps_main.

*** Bad machine code: No instruction at VNInfo def index ***
- function:    _amdgpu_ps_main
- basic block: %bb.3  (0xb021a08) [368B;400B)
- liverange:   [160r,160d:7)[208r,208d:6)[272r,272d:5)[320r,320d:4)[396r,396d:8)[464r,464d:3)[496r,496d:2)[624r,624d:1)[704r,704d:0) 0@704r 1@624r 2@496r 3@464r 4@320r 5@272r 6@208r 7@160r 8@396r
- regunit:     EXEC_LO_HI16
- ValNo:       8 (def 396r)

*** Bad machine code: Live segment doesn't end at a valid instruction ***
- function:    _amdgpu_ps_main
- basic block: %bb.3  (0xb021a08) [368B;400B)
- liverange:   [160r,160d:7)[208r,208d:6)[272r,272d:5)[320r,320d:4)[396r,396d:8)[464r,464d:3)[496r,496d:2)[624r,624d:1)[704r,704d:0) 0@704r 1@624r 2@496r 3@464r 4@320r 5@272r 6@208r 7@160r 8@396r
- regunit:     EXEC_LO_HI16
- segment:     [396r,396d:8)

*** Bad machine code: No instruction at VNInfo def index ***
- function:    _amdgpu_ps_main
- basic block: %bb.3  (0xb021a08) [368B;400B)
- liverange:   [160r,160d:7)[208r,208d:6)[272r,272d:5)[320r,320d:4)[396r,396d:8)[464r,464d:3)[496r,496d:2)[624r,624d:1)[704r,704d:0) 0@704r 1@624r 2@496r 3@464r 4@320r 5@272r 6@208r 7@160r 8@396r
- regunit:     EXEC_HI_LO16
- ValNo:       8 (def 396r)

*** Bad machine code: Live segment doesn't end at a valid instruction ***
- function:    _amdgpu_ps_main
- basic block: %bb.3  (0xb021a08) [368B;400B)
- liverange:   [160r,160d:7)[208r,208d:6)[272r,272d:5)[320r,320d:4)[396r,396d:8)[464r,464d:3)[496r,496d:2)[624r,624d:1)[704r,704d:0) 0@704r 1@624r 2@496r 3@464r 4@320r 5@272r 6@208r 7@160r 8@396r
- regunit:     EXEC_HI_LO16
- segment:     [396r,396d:8)

*** Bad machine code: No instruction at VNInfo def index ***
- function:    _amdgpu_ps_main
- basic block: %bb.3  (0xb021a08) [368B;400B)
- liverange:   [160r,160d:7)[208r,208d:6)[272r,272d:5)[320r,320d:4)[396r,396d:8)[464r,464d:3)[496r,496d:2)[624r,624d:1)[704r,704d:0) 0@704r 1@624r 2@496r 3@464r 4@320r 5@272r 6@208r 7@160r 8@396r
- regunit:     EXEC_HI_HI16
- ValNo:       8 (def 396r)

*** Bad machine code: Live segment doesn't end at a valid instruction ***
- function:    _amdgpu_ps_main
- basic block: %bb.3  (0xb021a08) [368B;400B)
- liverange:   [160r,160d:7)[208r,208d:6)[272r,272d:5)[320r,320d:4)[396r,396d:8)[464r,464d:3)[496r,496d:2)[624r,624d:1)[704r,704d:0) 0@704r 1@624r 2@496r 3@464r 4@320r 5@272r 6@208r 7@160r 8@396r
- regunit:     EXEC_HI_HI16
- segment:     [396r,396d:8)
LLVM ERROR: Found 6 machine code errors.
PLEASE submit a bug report to https://bugs.llvm.org/ and include the crash backtrace.
```
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJztWktz6rgS_jVko4KSZVu2FyyAkBOqAsmFTGbmblzGFuA5YFN-5OT8-9uS_AYbz2MzdUmlYrvV6lZ__aklOd6G3s_xr35yQMmBISdJHPfAPDTQpwmLE-Q6MRvojwNiHpLkHA_UyYA8we8eeqTbkRue4OF4_Mwvw3MU_sHcBB53_pHFcDUVk1qYwl3EvNRl3ij5gnYLLdCeJdwifhzgyYDi7Fc-Eg0NjHlu1mPbdA8PWz8QIhcNT07kHgbqo3Py9m4Az-45hcf97svCGA0_WeTvfoKWe_AD5gdxEsWoOgLpJnOmoskuYRHaLNCvh_DI0H9Sx0PL0GO5RtcvWqze5-uPycsGdStKY_Pf5jP75dV-XiiUI61QHA3IDC4ewGEANiAk2ORCuHAhzYQGEUKDcKEuhSoR3eHChVomtKgQWpQLTSnUqMaFcOFCNRNKTU1qEimkRGjChQsVKTSwEMKFCzHPIR5omIuRAje8EyJww00ild-AQ6TBDR8j0uGGR4Aov4H4kAE3PHpkch0-kBKg5wVgdAeoE6A7g1oA-vj2tsYFf_BUgBNVfeLp8Hzwq9o5mLe0B0THAnQrhzJXBaGuabw7xea02p_rIvSD-fsDL3l4hMUPG5ApLiqeTrhZVWKkqWRamhX2BJq1YXHd22Y1VGZOjK80a5CpzEfNrAD9plldMk8QTyE1AyC93V8V4xJdwYJRB5yLe0QmTKjCgkWnJSUVIrmv00q04qlANuOpeAKhiaOS-7ohwsqyqNRzYBTd5UjBlSAv7yTIy_1wuggCw-AEf7kfIbwdVG1KW01kcR9cDGFCRiHqQNWE0Sc7monKcqE2CCLm4G0TliCeibPqUOeY2ScQOdNELlXJkCwZqowNLl7b5FOKWcID5hkyb3lcs_3Sib_H5a6ke91fTmbPi9V8sdq8r_ut_XyrsZR7EuTC9gLtwgjt0sBN_DBANt_MnFP7HNsnB7Y66gStwrfnBeyjZug9ctzv8Yv_yQIWS4nPvNdzvGY_Ij9JWCBdPOXWuCpaBDwaGJv2uT9HGPkB4rhWtz9Q8LC13Y7waMSCJPpZRo8thOLUdcFfGGV2dNAEaE38pUkABfgwGtmkXzSp00ovncMOjxd9qg2l8yOE4NcjkK3mVLQLikBrHLG9TaEaqI9o9vr2O9dmX8yVygottUGZm7FVUlOumOYFIdPWtIbtjb18_bCn8DRUpDbVpPbGnk3Xk9Xs2d7MZkoZ2Az5p_PRd_0EpYHHdtxZ7GYDM3HeWfYtgKpkx6JZerhRWIZ1Pxpuj6H7fSTW-UquONJn2OKyi3zhG_mk7fkk7fmkbfkk1_MpUqGU6KpNdINwd2ZfLjsn6MOeLd_s1bd3-0klNgMFzO2Xf-q5LMQF2ADziW_fG7IKKYjZJ884pxAutWkX4yoOh1m-K06NkoqaceF0snoUThtOsnireF248RgcWKrcgpWjcNWcIhv7t9d14cm48NR03u2J4AJJEWodQRvOVacLP7IjuZg8fGf735JGbckj2vWZQ6tcE-u9mDpk9HQMfyj9JotSEpnemDdq-7wx2ueN2jZvjPZ5Q4xKVTIv0gnZ3Ew-5uJckKUVd6Swg6s8q62wwz6gGAXpYG9hvTHaNodZ3cXXaJQxNadR1TTpa1mlXTwzOgLWyVWeqdXcqNTMeKY2S7RCe9docoNrmiCUeY1QvEnB14mj5hUnm7aX66VI3IrkvGkS5wZXpJNiIVvY88n65Xf7fb5eLlaT9zlfDvElug3EK5Zu1xJcjY-fzST42t8AX70BvtEOvtEBvqbQq_Qxakpyw8G3C6JM9V3SK2Wje_Bme5Wy2quU2ValrPYqpdGyPjSX1P6LpGZW1lqrc5G8XLn-1BqpWbTXymU1Vy5dIV0VxWqvKHq-7WhQwqziKA4yghK0SWqi9Ca1coMXpJ3UpIPUenUP05llqW5dL6GkapPivIQaYg6QvjWzYKV2I1i9PVi9I1hKtGsMKXZPf2U5ovr1qlA7lFEjrwrmBQVIbwroN1Cx2lGxOlDJhmjmSbNGvwT-Dk6ja5akUTDlw-w7wCKDtRlg4P64d035Ku4GKTaN89Xj27dlfSXhR_N54KFT3-P5qN47fykwdeo25CkeiX9BpNKQAwec1SLYhYiP0Ydz4RdqvCgYFm55f_hpvhvItLZO7LtomyGeL2ccN0jsFhPFwfzdrXhPxvcp6lSsmHk-h-KIHTnBnkk_97fJl2-ThwjYlQZ-kqUCVf-Dk6t8OMdVmCsgJGYtz66M3OrPFfHaJmb7EwsS5IUsDgbESBADagJvHPTpHH2vRqc7df7d1MmSnatcj_lea_6PCZP9M_Rea-7U-ZvUudeaO2FuEua-r7lT5x-gTv9a8_LysUTz9fp1zZWfwhRIQesnMRZFcHLMzlxvL_PJZg5H2u3J59zZpnsY0DmMEpSEqP6tGrTFI_4V2SiM-DdkyAk4zdxjClb5V29u5MQHYI37PYkcl-XHuvyDtAdvrHqWajkPiZ8c2fjyGzHkOmnM4n-G9Q9pdBz_6a_t_DhOxed2ukYweTiMIcPEUzxqGYZueJrnqtiydjuPMFfRyRY_HJ0tO8ZjSMqAEB48DAk8TpaP395-AdFAf3zwx2CM8M9MoA_V1RF1tgpRVFdV3Z3hqA5wgsHUOxb4PkRjMTIOOjQe_TgpwX9w4tjfB4wJr2DfSZNDGI3_cH7uQsd7EEGMRQT_A20FRDM">