<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=http://email.email.llvm.org/c/eJylVUtv2zAM_jX2RUjgyHYTH3zo1hXYbUCHYbdBluhYmyx5euTx70fJSZcVxdJsgCGRlPnpE0VSnRHH9vMApDdKmb3UW_Ll6SuR2lupneSOCCmINp5oAEG8IXCQzuMPxEcvaVGZFOOQ0feEaRHNRzIGNHdALKQ1QYxFWbMRxe5IuNE7qaM9mhxxQXrWKYj4EXZk04SLyMDbwL002kUE5okChsijEbKXM5aF0ewi7-gYtAYOzjF7JG4Ifa_AZeV9VjxkxWlckB1wj2hObnXaxEfLt1nFY2xO68IEpJTRhiyy8gM57PhOTO6wd2_BMbfjBP0C6Wy4xincgHWN1ytYvTJsBknS1QhNf_e_Gpkr_hf7n86oDN5-HP5AcgdxA5X_hbpg9Rz718HCTbzeDjaP95wbK1I5zKWkkBtWTJgECsT05OPTPSmXqxdV8cnCTprgkIR1c731yZ9ZPkiPZIJFJfYISDUea9iD9unHTuJcUsS8K6MOjA-n290jnXO3sOCC8jhtsYWAjRS7WLMCeolnjB1kQHykkJqJUmSyJpazsQ4BMEQuTJOxHhXpLtsD2VskebkJJr75R15zRJgje0AKzF1gFQhVrhI7NDt0-RmknRtR4nQK32vRW-aiLUVTNixnwQ_Gtg7kD0MnFVwerGoH76fUregjflvph9AtuRlRUWp3nhYYk--IiKp0LmB_o4912aw2-dBCs6qooHXddRUA7ZuiKNZ8vVmXFW166HLFOlCuzep3GaUa9iRBoJzVD_n_M5AtLSh-q02xqWm5WZZN33PRc1rVq3XFWVYVMDKplhFnaew2t22C7MLW4aLCC3C_F5lL2Q-JMDL00itop4nfVciSYKZo3NsIQSawY_As5UKPdRMfsbtqgZcWs6ykSYrPzjm98a60SQWFifj8aOTpQG06zS8XzHHZ>53918</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            ppc64: even/odd permutation for VSX 64-bit to 32-bit conversions is no longer necessary
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          seiko2plus
      </td>
    </tr>
</table>

<pre>
    The following VSX intrinsics did not need to exist in the first place, and they must be replaced or renamed by convinced names suitable to the mapped instructions or at least modified by removing the unnecessary shuffles:

- vector signed int vec_signede(vector double) -> xvcvdpsxws
- vector signed int vec_signedo(vector double) -> xvcvdpsxws
- vector unsigned int vec_unsignede(vector double) -> xvcvdpuxws
- vector unsigned int vec_unsignedo(vector double) -> xvcvdpuxws
- vector float vec_floate(vector double) -> xvcvdpsp
- vector float vec_floato(vector double) -> xvcvdpsp
- vector float vec_floate(vector signed long long) -> xvcvsxdsp
- vector float vec_floato(vector signed long long) -> xvcvsxdsp
- vector float vec_floate(vector unsigned long long) -> xvcvuxdsp
- vector float vec_floato(vector unsigned long long) -> xvcvuxdsp

According to the latest update of ISA 3.1:

Previous versions of the architecture allowed the contents of bits 32:63 of each doubleword in the result register to be undefined, however, all processors that support this instruction write the result into bits 32:63 of each doubleword in the result register
as well as into bits 0:31, as is required by this version of the architecture.
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJylVE2P2yAQ_TX2BSWKIcnGBx-23a7UW6Wtqt4qDDimxeAykI9_3wEn23S1ajatZOGZwfPmMXhe6-Sx-dwr0jlj3F7bLfny9JVoG7y2oAUQqSWxLhCrlCTBEXXQEPADElKW9uiMhgtV0PeEW5nCRzJEDLeKeJX3JHEebcsHNNsjEc7utE3xFAICUQfeGpXwE-zAxxE3kUHwUQTtLCQEHohRHJEHJ3WnJyyvBrdLvFNitFYJBcD9kUAfu84oKNh9sXgoFqd1RnZKBEQDvbW5SEiRb5OLx9ic9qWLSKmgNZkV7AM57MROjnDYw1tw3O040b5AOgeucYo3YF3j9QpWZxyfQLJ1tUPj3_OvduZK_kX90xmNw9tPyx9IcJA3UPlfqAtWz71_HSzexOvtYNN6L4TzMo_DNEoGueHExFGiQVxHPj7dEzavXkzFJ6922kVAEh6meetyPvei1wHJRI9O0giVZzzNcFA25A9bjW9GEXPNkq-46E-3u0c6Z7XwCqIJ-NqihCifKLZpZqXqNJ4xKUiP-Eghi4kxZPQujbPzgADYIojj6HxAR8OlPJC9R5KXRfDHd__Ia-oIB7JXSIHDBdYCoViV2WEYMOVn1H4Soszp1L7XujcvZcNkzWpeBh2MasZRrJcISPDEtqCPTkoyKj_EwPOZOrz_JMbr5QyLp24xmq0kn-drwprW5R8DG_osfmX0pulDGLP60Ud8tjr0sZ0LN6BjzO78mmGPvyNDdDVARL2kjytWV5uyb9bVatV1sloLWlfIvWYb3i1ZvaB3bEnXqjS8VQaaYvWuoNSqPckQaBerh1I3dEHxqTaLzYqyzZzVXSdkJ-hyVd0tBS-WCzVwbeaJx9z5bembTKmNW8BNg9cBvzc55FlQuRzi8xh65xtQ-oejo4lQ5upNZv8LtsZb2A">