<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=http://email.email.llvm.org/c/eJylVsly3DYQ_ZqZC2pY3GY7zEFrSmU5SUWOnBxBssmBBQI0ANKSv94PIGnNKIl9iIri0gB6ef26ewpdvRyOznV2kV0s0ltcja4KLV2kTYOvr_i35tO7Mvt787yIrxfxxXj_cBSWSa071pGptWktc0dilXasM7rqS8d0zdwXzQYqnTaW9VaoJmwaJUwoZ4SyorQRuxeKWBKHM9hR6rYTkiq8VMQsOXt6UJJq3JHBapAa8uaEVsz2LbRaZ8ZvH9Po8iaervA5QOEgBZv_vpLRi_SK8dzfKdn4R5v6u-vDez8dhCnYiAY7Hhx2fnVIwlZ8_JuxjwKu4uvx_ubXRXadrjd-CfvxeLj5CFEyS7iqvPT-_Z_3fuckdR7pRgzkIRw1vb_4K2xIL4LW9HZUlPkjEbuoHY3IhPzUQgl7JOt13bFWDzShZnvpmNOMM1tyyQ1EjbD-7CLdyZAQxLefk7P9cR7gZNCtwQf-M_TFCfwz-vEp-EmInJ-B3w7Rc2S_Z43HP0D9kkreW2KFhoPGJgFbUzFuiD2_wooL0XdUCi4RlbGeRRMHoWt2Fa-nvPL4iJY3xGqj27D5j7uHq9UjewzKvmtKovgVhTRZrC_DscX6GhrOyw7OmlVYtVEDyvSFl5RaOVIuQj1gT5rm600KgG6TdZrt8ySPV-WG83qz3q9om29XOe2S1S7fblYVxSmlfJvm9S7qFGp5f1q-D0KV9IaCb_iXBNHEJQCl6MtZcY0Unsl4RsSgLmKXvfsOcyXqmgxiGTErCKwhcLUstalCY9ABSI_feXoWaQqukhmowisruaW5WPwB0XaSWigOpAPDfdoDU30ChZTeldPQ75jhiv3WuUthweOgqNZ9UBds2p4Y7zriaFqjn9jzAmI70Yqvo5mOW4tMwRyXVsPeWFSWtzRpEIr9cnUV_aNnojsWcBhxKGj30Vktp9iKF9Zy1XMpX3wI7k3DnOpt8skvhIo7SUrEPkCqFc6XR66a4IbfqHvXIRvC1y93QeTz-QOOH7lFwSCZ_E0mSem-OYbGMWhRTc3kcy9MSMNoINDCx6gwEEZXIvYAlH42bOj3d7v17nPx4RS4W6E8JiMvEIwRjZdM00G0veQO7REe0zP44zA4vqCGEDQjY8KoYQ-deArEqch2wo34-VVFGn31FMQzttgxcGRrzKtXzNqXYHuR3YIB3lBzdNOAu79_fB849TreWEscwNyhCCrUzdYBXN-FNXsi6oCSobqXzBlePs3d5yzlqJOZnlPGJ9WYt2RHlY4_gadskOhxTe8zEfopvCUTBS-Fenotq7NwriQSFLGbsJkJxyxCkmiY1GkzsmWmLZCcg4d6fbq7IeVbP00T3BhfXf_NsGhZHbJqn-35kvfA0BwwewZdcAz-l2Vv5NsfJqErTq1QymF-rODaJ5jCZwgJg-52na232-XxECfbmniyp7LYFZtqV9O-SuqkWufrMo13-VLygqQ9oDOj_kKH8yrwjh69_P8eiEMap7jiPF5n-yyL4rzc8vWe0iLPqmJXLfKYWkQceT2-DJbmEFQWfWOxKDGQ7esiuo5oFFFwGB464SQdpuEzUWb67WR8I_S8njMxp2EZfDwEB78BGtU-hg>53577</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            RISC-V vector compiler uses incorrect vsetivli
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          stevobailey
      </td>
    </tr>
</table>

<pre>
    https://godbolt.org/z/srjKc3Y6x

This loop performs the dot product of two vectors using the vector intrinsics. Line 10 of the compiled code sets the vector length for the reduction sum instruction:
```
vsetvli         zero, a4, e16, m2, tu, mu
vredsum.vs      v8, v12, v8
```
With `VLEN=256`, `SEW=16`, and `LMUL=2`, this gives us `VLMAX=2*VLEN/SEW=32`. After the loop finishes, I move the result to a scalar register (line 18). Line 17 sets the vector length for this move operation:
```
vsetivli        zero, 0, e16, m1, ta, mu
vmv.x.s         a0, v8
```
Because both rs1 and rd are x0, this is a special version of the `vsetivli` instruction (image from the RISC-V V spec version 1.0:

Since `SEW=16` and `LMUL=1` after this new instruction, `VLMAX=VLEN/SEW=16`. But this is different from before. According to the spec, this is a "reserved" case, and the implementation I use sets `vill`.

I ran OptBisect and found this issue appears before any optimization passes. I also see the same issue in GCC.

This problem can be "solved" by manually setting the vector length before the move instruction. The only change in the output is that the new `vsetivli` instruction has rd=a0. But this is enough to avoid the requirement that VLMAX cannot change. See https://godbolt.org/z/ePK858qbT

Finally, the original code simulates as expected without error in Spike, despite the erroneous instruction.

Is this an issue with my code? I thought using LLVM and intrinsics meant I didn't have to keep careful track of the vector length. And this move intrinsic doesn't take a vl argument, either. I think this is an issue with Clang. Either it should report the problem in my code, or it should generate the correct `vsetivli` instruction.
</pre>
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