<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=http://email.email.llvm.org/c/eJzNVNtu2zgQ_Rr5ZWCBpqLYftCDGydFgBQtFtgPoERK4priCLzYcb--Q0lp0nax7WKBYgGB5Aw5lzM6MzXKa9WHMPqsOGT8gb5Ohz7WeYMDCcacX7b16PAv1QQSa4M1bYPQNm1GO9qC8unu0QbVORE0prv3n_6k9Y-Pdx_SiwuuB5TRKJ8nIxBWwu8KfiZrdOvghPWtcjguOWT8Di69bnoQToHUPmjbRe17JaF1OEDoFSAtDlIQD9qSSgSoRSCj-gq9OJMJDEj2dGMBrYKTclYZGJ3yyoYUpBXawIXwgXIOnQcfU1A_BWjRGLyQm4wdM3ZY1lu2fJNoZG6MpFLNDtLBE6iElY65vFox6Aa0B4sBGrRBdxGjn4POEJwyDl_M_M_8Qh7Uc4CzdiEKA0JKguOBSthRTc7KGTEu7nOHUgSxJF7cz9_iYDagxLLyHXve3DKWCpJOfJuVxx-MZl__YFY8vJr9GgaDQv5PARR30Z4sXuxkfWDfoCBUxLgzNhOpF_3fsWNZ-a5FN1FK1ARwYl0k0ClwesvLptcjnaa0blnXPu_ZbrrZ5994umGiE1YJ8No2Cq4Y4aKI4mjftMTT0xGafoI5N4XDkwLiXGrtQXd9gARtbg7KKAboSQw9Re_FOCpLbbYG3cJjxreUL4VdkypFuDikthqV86mb70CMaLDTNDxWsirkvtiLlYihR1ed3Oer_8zYKjrz78eZ9j6mCj2Uxc22XPUVu73Z1OW-bFq-vSl5I1nNarHft7zdbrisV0bUyviKfmvGeR07WqcCc55Y-FWoRXNSNtHy8OE4TaO3z4rD_dPDq2qaZMVhTvE7ZTfG73QklcfVfwerK844Zxu-40WxK7Z5sZOqFE2rdptClXVNP0TRrDV58pOj61aumlwSbE-Xhiamf70U3uvOKjXVhjIMOhhV0QweiMZfh_MyShM50-jUM6XmYemJWy0M0QQ9mpdB6ldT3tWU9BfmACGD>53475</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            ROCm integration tests failing in the presense of multiple kernels
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            bug,
            lld,
            backend:AMDGPU,
            lld:ELF,
            mlir:llvm,
            mlir:gpu,
            mlir
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          krzysz00
      </td>
    </tr>
</table>

<pre>
    https://github.com/llvm/llvm-project/blob/main/mlir/test/Integration/GPU/ROCM/two-modules.mlir and https://github.com/llvm/llvm-project/blob/main/mlir/test/Integration/GPU/ROCM/vector-transferops.mlir , which are distinguished from the other tests in that batch by having more than one kernel present, fail with errors such as the following

```
ld.lld: error: section: .dynamic is not contiguous with other relro sections
ld.lld: error: section .text virtual address range overlaps with .rodata
>>> .text range is [0x1600, 0x1627]
>>> .rodata range is [0x1600, 0x163F]

ld.lld: error: section .text load address range overlaps with .rodata
>>> .text range is [0x1600, 0x1627]
>>> .rodata range is [0x1600, 0x163F]
<unknown>:0: error: lld invocation error
```

(for the above failures, `%chip` is `gfx908`).

@aganea since you were on the other LLD change that broke us and might know more about how this happened - if I've @-ed the wrong person, apologies.
</pre>
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