<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=http://email.email.llvm.org/c/eJylVdtu2zAM_RrlhbAhy0kcP_ghTbGiGLYBRX9AtmhHhWxlkpym-_pRdi9psHUbFtiKRFLUIXlE11Y9VfsQDp7lWyY-0dNZVVsTUus6Wv2g97PclDffb9oHxq8Z387j_V57kG2LTfBwQNda18uhQaAJbO--5AKwr1EpVOCffMDep-f7v1roZQjo4HEvA7RGdh5uodnLoUMmdnEuBxjwSCYdBgh7BId-NEEPHbA1N8rRCMHC6BHIlq2udN-j0jIg2Lb1GNjqmonN-wAVuTSWIKfS9Wlj-yizzdjjEGTQdojrUfNlkdPsgV6yS-SgkrAf-zrRgw9ubKKlJyXBSJLXc5P53ISJMoXbAB4p8IhRmkf55KFGoAiVoawctYyo8RScpMg67WM2enucwicjOBPPbt9lcGcoVZAtU57ymI_k2w9IesJKY3MYWX5N8yKoXkdxraNAHhpPps9uaDI90vezhA6H-HNZhMBEnq1nhfFmVvComEdSi1lrnTvb9rp5ycuX7cqdbac6PfvJYn0mi_o0GYBxF9he2IZU4_Bo4Tz70NjRqJhTqmKtB0qqHmKuwRNHDIKxkkQXnEj_Ofo0Tf82jgvc83iHycFZNTaRuTsCqzCy8f2GZl5TAFR1qYi2carViagErLia1fH0hkIPcLSG2EpBkhkT22fp9fZ-C1Rpgr_5jWH0x08ZzzjLz7w6DKMbJgfxItG5FNOLASs-iu9mt4M5QPTTPVXotaNq2DEcxvesjbaZeOOs_1_OfkxNqdSvtH-k5lz9P7JzoapclXkpF3IMe-uqFo0-PdgB_WJ05rK1auog9XPLMeb48hfZ8UCNlJba-xFjW1nlgtzvK8k5Nq3KVmvEkq_zdrPKuCoLvtlgWZbNwsgaja8IORNiwEeYXNCc0C_-H4GuBBeCZ1lBOV1SVys2dS2zZoVrUdTFWrAlx15qk0Y_8auxcNXksh47T0pDDcy_KaX3uhsQJ8CEMOhgsJo_GF9toF4eL8nlnV1MqKoJ0k9C1ffD>53260</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            ARM32 Not using immediate offset
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          felixjones
      </td>
    </tr>
</table>

<pre>
    https://godbolt.org/z/Ka89GqGfj

This affects performance for ARM32 embedded systems.

No matter what flags I change, I can never get the resulting `ldr` to use an [immediate offset](https://developer.arm.com/documentation/dui0473/j/arm-and-thumb-instructions/ldr--immediate-offset-). It seems to always be handled via an extra register move, and a register offset.

Clang 14.0.0 `-Oz -marm -mcpu=arm7tdmi -mabi=aapcs`
```asm
mov     r1, #16
lsl     r0, r0, #2
orr     r1, r1, #4096
ldr     r0, [r0, r1]
bx      lr
```
These two instructions could be combined into a single load immediate offset.
```asm
mov     r1, #16
...
ldr     r0, [r0, r1]
```

Re-producing C code:
```c
int read(int idx) {
    const volatile int* const DATA = ( const volatile int* ) 0x1010;
    return DATA[idx];
}
```

GCC produces the desired output.

GCC 12.0.0 `-Os -marm -mcpu=arm7tdmi -mabi=aapcs`
```asm
lsl     r0, r0, #2
add     r0, r0, #4096
ldr     r0, [r0, #16]
bx      lr
```
</pre>
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