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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [InstCombine] try harder to peek through vector bitcasts with bitwise logic"
href="https://bugs.llvm.org/show_bug.cgi?id=52351">52351</a>
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<th>Summary</th>
<td>[InstCombine] try harder to peek through vector bitcasts with bitwise logic
</td>
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<th>Product</th>
<td>libraries
</td>
</tr>
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<th>Version</th>
<td>trunk
</td>
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>All
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<th>Status</th>
<td>NEW
</td>
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<th>Severity</th>
<td>enhancement
</td>
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>Scalar Optimizations
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>spatel+llvm@rotateright.com
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<th>CC</th>
<td>llvm-bugs@lists.llvm.org
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<p>
<div>
<pre>Vector bitcasts can interfere with bitwise logic reductions:
define <2 x i64> @src(<2 x i64> %x, <4 x i32> %y, <4 x i32> %z) {
%yb = bitcast <4 x i32> %y to <2 x i64>
%yz = and <4 x i32> %z, %y
%yzb = bitcast <4 x i32> %yz to <2 x i64>
%xy = and <2 x i64> %yb, %x
%r = or <2 x i64> %xy, %yzb
ret <2 x i64> %r
}
define <2 x i64> @tgt(<2 x i64> %x, <4 x i32> %y, <4 x i32> %z) {
%xb = bitcast <2 x i64> %x to <4 x i32>
%xz = or <4 x i32> %xb, %z
%xyz = and <4 x i32> %xz, %y
%r = bitcast <4 x i32> %xyz to <2 x i64>
ret <2 x i64> %r
}
<a href="https://alive2.llvm.org/ce/z/dWQbwD">https://alive2.llvm.org/ce/z/dWQbwD</a></pre>
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