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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - convert shifts and logic to popcount"
href="https://bugs.llvm.org/show_bug.cgi?id=52092">52092</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>convert shifts and logic to popcount
</td>
</tr>
<tr>
<th>Product</th>
<td>libraries
</td>
</tr>
<tr>
<th>Version</th>
<td>trunk
</td>
</tr>
<tr>
<th>Hardware</th>
<td>PC
</td>
</tr>
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<th>OS</th>
<td>All
</td>
</tr>
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<th>Status</th>
<td>NEW
</td>
</tr>
<tr>
<th>Severity</th>
<td>enhancement
</td>
</tr>
<tr>
<th>Priority</th>
<td>P
</td>
</tr>
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<th>Component</th>
<td>Scalar Optimizations
</td>
</tr>
<tr>
<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
<tr>
<th>Reporter</th>
<td>spatel+llvm@rotateright.com
</td>
</tr>
<tr>
<th>CC</th>
<td>llvm-bugs@lists.llvm.org
</td>
</tr></table>
<p>
<div>
<pre>define i32 @src(i32 %0) {
%2 = lshr i32 %0, 1
%3 = xor i32 %2, %0
%4 = lshr i32 %0, 2
%5 = xor i32 %3, %4
%6 = lshr i32 %0, 3
%7 = xor i32 %5, %6
%8 = and i32 %7, 1
ret i32 %8
}
define i32 @tgt(i32 %0) {
%2 = and i32 %0, 15
%3 = tail call i32 @llvm.ctpop.i32(i32 %2)
%4 = and i32 %3, 1
ret i32 %4
}
declare i32 @llvm.ctpop.i32(i32)
<a href="https://alive2.llvm.org/ce/z/bWgS_h">https://alive2.llvm.org/ce/z/bWgS_h</a>
This example is derived from the post-commit discussion in:
<a href="https://reviews.llvm.org/D110170">https://reviews.llvm.org/D110170</a>
The number of masked bits is not limited to 4 specifically, and those bits
don't have to be sequential. There's likely some related transforms for 'and'
or 'or' rather than 'xor'.
This may not be a win in codegen for a target that doesn't support popcount, so
backend work may be needed if this is implemented in IR.
Since the pattern is not limited to a fixed number of bits/ops, this could be
tried in AggressiveInstCombine to avoid compile-time concerns.</pre>
</div>
</p>
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