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<base href="https://bugs.llvm.org/">
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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - Module artifact file size grows exponentially with depth of imported modules and -Xclang -detailed-preprocessing-record"
href="https://bugs.llvm.org/show_bug.cgi?id=52034">52034</a>
</td>
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<th>Summary</th>
<td>Module artifact file size grows exponentially with depth of imported modules and -Xclang -detailed-preprocessing-record
</td>
</tr>
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<th>Product</th>
<td>clang
</td>
</tr>
<tr>
<th>Version</th>
<td>unspecified
</td>
</tr>
<tr>
<th>Hardware</th>
<td>PC
</td>
</tr>
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<th>OS</th>
<td>Linux
</td>
</tr>
<tr>
<th>Status</th>
<td>NEW
</td>
</tr>
<tr>
<th>Severity</th>
<td>normal
</td>
</tr>
<tr>
<th>Priority</th>
<td>P
</td>
</tr>
<tr>
<th>Component</th>
<td>Modules
</td>
</tr>
<tr>
<th>Assignee</th>
<td>unassignedclangbugs@nondot.org
</td>
</tr>
<tr>
<th>Reporter</th>
<td>thonerma@synopsys.com
</td>
</tr>
<tr>
<th>CC</th>
<td>dgregor@apple.com, llvm-bugs@lists.llvm.org, richard-llvm@metafoo.co.uk
</td>
</tr></table>
<p>
<div>
<pre>While working to reduce a Clang modules related test case, I happened to notice
that module artifact file size increased exponentially based on the depth of
the imported module DAG, even for importing modules that contain nothing other
than an import for a dependent module. This seems to occur for at least LLVM
Clang 9 -12 on Linux x86_64. The files are not created as sparse files, so
their size does not appear to be an artifact of intentional holes. This only
appears to happen when '-Xclang -detailed-preprocessing-record' is passed.
A test case follows.
$ cat t.cpp
#include <M20.h>
$ cat include/M20.h
#include <M19.h>
$ cat include/M19.h
#include <M18.h>
$ cat include/M18.h
#include <M17.h>
$ cat include/M17.h
#include <M16.h>
$ cat include/M16.h
#include <M15.h>
$ cat include/M15.h
#include <M14.h>
$ cat include/M14.h
#include <M13.h>
$ cat include/M13.h
#include <M12.h>
$ cat include/M12.h
#include <M11.h>
$ cat include/M11.h
#include <M10.h>
$ cat include/M10.h
#include <M09.h>
$ cat include/M09.h
#include <M08.h>
$ cat include/M08.h
#include <M07.h>
$ cat include/M07.h
#include <M06.h>
$ cat include/M06.h
#include <M05.h>
$ cat include/M05.h
#include <M04.h>
$ cat include/M04.h
#include <M03.h>
$ cat include/M03.h
#include <M02.h>
$ cat include/M02.h
#include <M01.h>
$ cat include/M01.h
#include <stdint.h>
$ cat include/module.modulemap
module M20 {
header "M20.h"
export *
}
module M19 {
header "M19.h"
export *
}
module M18 {
header "M18.h"
export *
}
module M17 {
header "M17.h"
export *
}
module M16 {
header "M16.h"
export *
}
module M15 {
header "M15.h"
export *
}
module M14 {
header "M14.h"
export *
}
module M13 {
header "M13.h"
export *
}
module M12 {
header "M12.h"
export *
}
module M11 {
header "M11.h"
export *
}
module M10 {
header "M10.h"
export *
}
module M09 {
header "M09.h"
export *
}
module M08 {
header "M08.h"
export *
}
module M07 {
header "M07.h"
export *
}
module M06 {
header "M06.h"
export *
}
module M05 {
header "M05.h"
export *
}
module M04 {
header "M04.h"
export *
}
module M03 {
header "M03.h"
export *
}
module M02 {
header "M02.h"
export *
}
module M01 {
header "M01.h"
export *
}
$ clang --version
clang version 12.0.1
Target: x86_64-unknown-linux-gnu
Thread model: posix
$ clang -Xclang -fmodules-cache-path=clang-module-cache -Xclang
-detailed-preprocessing-record -fmodules -Iinclude -c t.cpp
$ ls -l clang-module-cache/AK6XH28A43YE/
total 394356
-rw-r--r-- 1 thonerma sigeng 114300 Oct 1 15:54 M01-26DRXPGEC18LR.pcm
-rw-r--r-- 1 thonerma sigeng 52564 Oct 1 15:54 M02-26DRXPGEC18LR.pcm
-rw-r--r-- 1 thonerma sigeng 53520 Oct 1 15:54 M03-26DRXPGEC18LR.pcm
-rw-r--r-- 1 thonerma sigeng 55096 Oct 1 15:54 M04-26DRXPGEC18LR.pcm
-rw-r--r-- 1 thonerma sigeng 58200 Oct 1 15:54 M05-26DRXPGEC18LR.pcm
-rw-r--r-- 1 thonerma sigeng 64384 Oct 1 15:54 M06-26DRXPGEC18LR.pcm
-rw-r--r-- 1 thonerma sigeng 76708 Oct 1 15:54 M07-26DRXPGEC18LR.pcm
-rw-r--r-- 1 thonerma sigeng 101324 Oct 1 15:54 M08-26DRXPGEC18LR.pcm
-rw-r--r-- 1 thonerma sigeng 150512 Oct 1 15:54 M09-26DRXPGEC18LR.pcm
-rw-r--r-- 1 thonerma sigeng 248860 Oct 1 15:54 M10-26DRXPGEC18LR.pcm
-rw-r--r-- 1 thonerma sigeng 445500 Oct 1 15:54 M11-26DRXPGEC18LR.pcm
-rw-r--r-- 1 thonerma sigeng 838756 Oct 1 15:54 M12-26DRXPGEC18LR.pcm
-rw-r--r-- 1 thonerma sigeng 1625224 Oct 1 15:54 M13-26DRXPGEC18LR.pcm
-rw-r--r-- 1 thonerma sigeng 3198128 Oct 1 15:54 M14-26DRXPGEC18LR.pcm
-rw-r--r-- 1 thonerma sigeng 6343892 Oct 1 15:54 M15-26DRXPGEC18LR.pcm
-rw-r--r-- 1 thonerma sigeng 12635388 Oct 1 15:54 M16-26DRXPGEC18LR.pcm
-rw-r--r-- 1 thonerma sigeng 25218340 Oct 1 15:54 M17-26DRXPGEC18LR.pcm
-rw-r--r-- 1 thonerma sigeng 50384204 Oct 1 15:54 M18-26DRXPGEC18LR.pcm
-rw-r--r-- 1 thonerma sigeng 100715888 Oct 1 15:54 M19-26DRXPGEC18LR.pcm
-rw-r--r-- 1 thonerma sigeng 201379228 Oct 1 15:54 M20-26DRXPGEC18LR.pcm
-rw-r--r-- 1 thonerma sigeng 33072 Oct 1 15:54 modules.idx</pre>
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