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    <head>
      <base href="https://bugs.llvm.org/">
    </head>
    <body><table border="1" cellspacing="0" cellpadding="8">
        <tr>
          <th>Bug ID</th>
          <td><a class="bz_bug_link 
          bz_status_NEW "
   title="NEW - Unrecognized rotate patterns"
   href="https://bugs.llvm.org/show_bug.cgi?id=51748">51748</a>
          </td>
        </tr>

        <tr>
          <th>Summary</th>
          <td>Unrecognized rotate patterns
          </td>
        </tr>

        <tr>
          <th>Product</th>
          <td>libraries
          </td>
        </tr>

        <tr>
          <th>Version</th>
          <td>trunk
          </td>
        </tr>

        <tr>
          <th>Hardware</th>
          <td>PC
          </td>
        </tr>

        <tr>
          <th>OS</th>
          <td>Linux
          </td>
        </tr>

        <tr>
          <th>Status</th>
          <td>NEW
          </td>
        </tr>

        <tr>
          <th>Severity</th>
          <td>enhancement
          </td>
        </tr>

        <tr>
          <th>Priority</th>
          <td>P
          </td>
        </tr>

        <tr>
          <th>Component</th>
          <td>Scalar Optimizations
          </td>
        </tr>

        <tr>
          <th>Assignee</th>
          <td>unassignedbugs@nondot.org
          </td>
        </tr>

        <tr>
          <th>Reporter</th>
          <td>david.bolvansky@gmail.com
          </td>
        </tr>

        <tr>
          <th>CC</th>
          <td>llvm-bugs@lists.llvm.org
          </td>
        </tr></table>
      <p>
        <div>
        <pre>unsigned rol1(unsigned x, int y)
{
        return (x << y) | (x >> (64-y)); 


define dso_local i32 @rol1(i32 %0, i32 %1) local_unnamed_addr #0 {
  %3 = shl i32 %0, %1
  %4 = sub nsw i32 64, %1
  %5 = lshr i32 %0, %4
  %6 = or i32 %5, %3
  ret i32 %6
}

--------------------------------

define i32 @src(i32 %0, i32 %1) {
%2:
  %3 = shl i32 %0, %1
  %4 = sub nsw i32 64, %1
  %5 = lshr i32 %0, %4
  %6 = or i32 %5, %3
  ret i32 %6
}
=>
define i32 @tgt(i32 %0, i32 %1) {
%2:
  %3 = fshl i32 %0, i32 %0, i32 %1
  ret i32 %3
}

<a href="https://alive2.llvm.org/ce/z/6jDaR_">https://alive2.llvm.org/ce/z/6jDaR_</a></pre>
        </div>
      </p>


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