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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [AArch64][MIScheduler] UseAA incorrectly reordering struct load and store that alias"
href="https://bugs.llvm.org/show_bug.cgi?id=51627">51627</a>
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<th>Summary</th>
<td>[AArch64][MIScheduler] UseAA incorrectly reordering struct load and store that alias
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<th>Product</th>
<td>new-bugs
</td>
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<th>Version</th>
<td>trunk
</td>
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>All
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<th>Status</th>
<td>NEW
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<th>Severity</th>
<td>normal
</td>
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>new bugs
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>cameron.mcinally@nyu.edu
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<th>CC</th>
<td>david.green@arm.com, htmldeveloper@gmail.com, llvm-bugs@lists.llvm.org, Paul.Walker@arm.com
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<pre>Created <span class=""><a href="attachment.cgi?id=25194" name="attach_25194" title="Reduced test case">attachment 25194</a> <a href="attachment.cgi?id=25194&action=edit" title="Reduced test case">[details]</a></span>
Reduced test case
The attached test case miscompiles at -O1:
<span class="quote">> llc test.ll -O1 -mcpu=carmel</span >
This is a regression, found in release/13.x, from this commit:
<span class="quote">>commit af342f72400445b85c38ba768439c495d7cf346f
>Author: David Green <<a href="mailto:david.green@arm.com">david.green@arm.com</a>>
>Date: Sat Apr 24 17:51:50 2021 +0100</span >
>
<span class="quote">>[AArch64] Enable UseAA globally in the AArch64 backend</span >
>
<span class="quote">>This is similar to D69796 from the ARM backend. We remove the UseAA
>feature, enabling it globally in the AArch64 backend. This should in
>general be an improvement allowing the backend to reorder more
>instructions in scheduling and codegen, and enabling it by default helps
>to improve the testing of the feature, not making it cpu-specific. A
>debugging option is added instead for testing.</span >
The Machine Instruction Scheduler is reordering a load and store that alias:
.Ltmp2:
adrp x8, .S01101
add x8, x8, :lo12:.S01101
ldr w9, [x8]
str w9, [sp, #8]
ldrb w8, [x8, #4]
ldr x0, [sp, #8] <== HERE
strb w8, [sp, #12] <== AND HERE
bl foo
mov w0, wzr
ldr x30, [sp], #16 // 8-byte Folded Reload
ret
The 8b store to sp+12 should happen before the 64b load from sp+8.</pre>
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