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<base href="https://bugs.llvm.org/">
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<body><table border="1" cellspacing="0" cellpadding="8">
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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - Failure to vectorize llvm.isnan calls"
href="https://bugs.llvm.org/show_bug.cgi?id=51556">51556</a>
</td>
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<tr>
<th>Summary</th>
<td>Failure to vectorize llvm.isnan calls
</td>
</tr>
<tr>
<th>Product</th>
<td>libraries
</td>
</tr>
<tr>
<th>Version</th>
<td>trunk
</td>
</tr>
<tr>
<th>Hardware</th>
<td>PC
</td>
</tr>
<tr>
<th>OS</th>
<td>Windows NT
</td>
</tr>
<tr>
<th>Status</th>
<td>NEW
</td>
</tr>
<tr>
<th>Severity</th>
<td>enhancement
</td>
</tr>
<tr>
<th>Priority</th>
<td>P
</td>
</tr>
<tr>
<th>Component</th>
<td>Scalar Optimizations
</td>
</tr>
<tr>
<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
<tr>
<th>Reporter</th>
<td>llvm-dev@redking.me.uk
</td>
</tr>
<tr>
<th>CC</th>
<td>a.bataev@hotmail.com, florian_hahn@apple.com, llvm-bugs@lists.llvm.org, sepavloff@gmail.com, spatel+llvm@rotateright.com
</td>
</tr></table>
<p>
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<pre>As well as missing Intrinsic::isnan from llvm::isTriviallyVectorizable, the SLP
call vectorization fails as we don't properly account for calls that have
different return/arg types - LV seems to have the same problem but I haven't
looked at that in detail.
opt -mtriple=x86_64-- -mcpu=btver2 -slp-vectorizer
define void @vec_isnan_f64(double* %a, double* %b, double* %c, double* %d) {
; CHECK-LABEL: @vec_isnan_f64(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[AIDX1:%.*]] = getelementptr inbounds double, double*
[[A:%.*]], i64 1
; CHECK-NEXT: [[A0:%.*]] = load double, double* [[A]], align 8
; CHECK-NEXT: [[A1:%.*]] = load double, double* [[AIDX1]], align 8
; CHECK-NEXT: [[TMP0:%.*]] = bitcast double* [[B:%.*]] to <2 x double>*
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x double>, <2 x double>* [[TMP0]],
align 8
; CHECK-NEXT: [[TMP2:%.*]] = bitcast double* [[C:%.*]] to <2 x double>*
; CHECK-NEXT: [[TMP3:%.*]] = load <2 x double>, <2 x double>* [[TMP2]],
align 8
; CHECK-NEXT: [[ISNAN0:%.*]] = tail call i1 @llvm.isnan.f64(double [[A0]])
; CHECK-NEXT: [[ISNAN1:%.*]] = tail call i1 @llvm.isnan.f64(double [[A1]])
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i1> poison, i1 [[ISNAN0]],
i32 0
; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x i1> [[TMP4]], i1 [[ISNAN1]],
i32 1
; CHECK-NEXT: [[TMP6:%.*]] = select <2 x i1> [[TMP5]], <2 x double>
[[TMP1]], <2 x double> [[TMP3]]
; CHECK-NEXT: [[TMP7:%.*]] = bitcast double* [[D:%.*]] to <2 x double>*
; CHECK-NEXT: store <2 x double> [[TMP6]], <2 x double>* [[TMP7]], align 8
; CHECK-NEXT: ret void
;
entry:
%aidx1 = getelementptr inbounds double, double* %a, i64 1
%bidx1 = getelementptr inbounds double, double* %b, i64 1
%cidx1 = getelementptr inbounds double, double* %c, i64 1
%didx1 = getelementptr inbounds double, double* %d, i64 1
%a0 = load double, double* %a, align 8
%b0 = load double, double* %b, align 8
%c0 = load double, double* %c, align 8
%a1 = load double, double* %aidx1, align 8
%b1 = load double, double* %bidx1, align 8
%c1 = load double, double* %cidx1, align 8
%isnan0 = tail call i1 @llvm.isnan.f64(double %a0)
%isnan1 = tail call i1 @llvm.isnan.f64(double %a1)
%r0 = select i1 %isnan0, double %b0, double %c0
%r1 = select i1 %isnan1, double %b1, double %c1
store double %r0, double* %d, align 8
store double %r1, double* %didx1, align 8
ret void
}
declare i1 @llvm.isnan.f64(double)</pre>
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