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<base href="https://bugs.llvm.org/">
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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [SchedModel] Missing ReadAdvance for MULX and ADCX/ADOX instructions"
href="https://bugs.llvm.org/show_bug.cgi?id=51494">51494</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>[SchedModel] Missing ReadAdvance for MULX and ADCX/ADOX instructions
</td>
</tr>
<tr>
<th>Product</th>
<td>libraries
</td>
</tr>
<tr>
<th>Version</th>
<td>trunk
</td>
</tr>
<tr>
<th>Hardware</th>
<td>PC
</td>
</tr>
<tr>
<th>OS</th>
<td>Windows NT
</td>
</tr>
<tr>
<th>Status</th>
<td>NEW
</td>
</tr>
<tr>
<th>Severity</th>
<td>enhancement
</td>
</tr>
<tr>
<th>Priority</th>
<td>P
</td>
</tr>
<tr>
<th>Component</th>
<td>Backend: X86
</td>
</tr>
<tr>
<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
<tr>
<th>Reporter</th>
<td>andrea.dibiagio@gmail.com
</td>
</tr>
<tr>
<th>CC</th>
<td>craig.topper@gmail.com, llvm-bugs@lists.llvm.org, llvm-dev@redking.me.uk, pengfei.wang@intel.com, spatel+llvm@rotateright.com
</td>
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<p>
<div>
<pre>Example:
mulxl (%rdi), %eax, %edx
```
<span class="quote">> llvm-mca -mcpu=haswell -timeline -iterations=2</span >
```
Timeline view:
0123456789
Index 0123456789 0
[0,0] DeeeeeeeeeER . . mulxl (%rdi), %eax, %edx
[1,0] . D=======eeeeeeeeeER mulxl (%rdi), %eax, %edx
```
There is a dependency on EDX (which is both implicitly read and written).
However, the load uOP can start in advance.
If I add a read-advance for the implicit read of EDX, I get this:
```
Timeline view:
012345
Index 0123456789
[0,0] DeeeeeeeeeER . mulxl (%rdi), %eax, %edx
[1,0] . D==eeeeeeeeeER mulxl (%rdi), %eax, %edx
```
NOTE:
Zen models override the (list of) Sched Reads/Writes for MULX32/MULX64 using an
InstRW. For those models, fixing this issue in X86InstrArithmetic.td would not
be enough.
When possible, models should try not to use InstRW. In this case, it is
probably better to just introduce a new Write definition specifically for MULX
(i.e. instead of reusing WriteIMul32/WriteIMul64). But this would be the goal
of a separate patch.
--
The problem with ADCX/ADOX is similar to the issue reported as <a class="bz_bug_link
bz_status_RESOLVED bz_closed"
title="RESOLVED FIXED - [SchedModel] Missing ReadAdvance for the source (non dest) operand of RMW instructions."
href="show_bug.cgi?id=51322">bug 51322</a> for
the ADC/SBB.
Example
```
adcx (%rdi), %rcx
```
<span class="quote">> llvm-mca adcx.s -mcpu=znver2 -timeline -iterations=2</span >
```
Timeline view:
012
Index 0123456789
[0,0] DeeeeeER . . adcxq (%rdi), %rcx
[1,0] D=====eeeeeER adcxq (%rdi), %rcx
```
The second load could start a few cycles earlier. For what I can see, we are
just missing a read-advance for the implicit read of EFLAGS.
NOTE: the same issue is reproducible on various other cpus (i.e. not just
znver2)
In theory, this is how the timeline should look like:
```
Timeline view:
Index 012345678
[0,0] DeeeeeER. adcxq (%rdi), %rcx
[1,0] D=eeeeeER adcxq (%rdi), %rcx
```</pre>
</div>
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