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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [AMDGPU][MC][GFX10][DOC] Correct description of MIMG address alignment"
href="https://bugs.llvm.org/show_bug.cgi?id=51388">51388</a>
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<th>Summary</th>
<td>[AMDGPU][MC][GFX10][DOC] Correct description of MIMG address alignment
</td>
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<th>Product</th>
<td>libraries
</td>
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<th>Version</th>
<td>trunk
</td>
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>Windows NT
</td>
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<th>Status</th>
<td>NEW
</td>
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<th>Severity</th>
<td>enhancement
</td>
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>Backend: AMDGPU
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>d-pre@mail.ru
</td>
</tr>
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<th>CC</th>
<td>llvm-bugs@lists.llvm.org
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<p>
<div>
<pre>For historical reasons MIMG address operand size must be aligned to be 16 (for
sizes greater than 8) or 8 (for sizes in the range from 5 to 7). However,
recent changes made alignment unnecessary for GFX10. See the following commits:
<a href="https://reviews.llvm.org/D103672">https://reviews.llvm.org/D103672</a>
<a href="https://reviews.llvm.org/D103800">https://reviews.llvm.org/D103800</a>
<a href="https://reviews.llvm.org/D103733">https://reviews.llvm.org/D103733</a>
This should be reflected in assembler description. For example, see the
description of vaddr operand of image_atomic_add:
<a href="https://llvm.org/docs/AMDGPU/AMDGPUAsmGFX10.html#mimg">https://llvm.org/docs/AMDGPU/AMDGPUAsmGFX10.html#mimg</a>
The description states that "the size is 1, 2, 3, 4, 8 or 16 dwords. Note that
assembler currently supports a limited range of register sequences." This is no
longer valid.</pre>
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