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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [Arm32] Atomic operations on 64-bit operations have invalid bit-cast"
href="https://bugs.llvm.org/show_bug.cgi?id=50721">50721</a>
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<th>Summary</th>
<td>[Arm32] Atomic operations on 64-bit operations have invalid bit-cast
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<th>Product</th>
<td>libraries
</td>
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<th>Version</th>
<td>trunk
</td>
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>Linux
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<th>Status</th>
<td>NEW
</td>
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<th>Severity</th>
<td>enhancement
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>Backend: ARM
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>rengolin@gmail.com
</td>
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<th>CC</th>
<td>llvm-bugs@lists.llvm.org, smithp352@googlemail.com, Ties.Stuij@arm.com
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<p>
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<pre>As demonstrated by <a href="https://reviews.llvm.org/D104264">https://reviews.llvm.org/D104264</a>, the ARM back-end generates
a pointer bit-cast from i64 value to an i8* (to a {i32, i32} struct) to call
the double-word atomic operations on, but if the pointer is in a different
address space, the bit-cast fails.
The back-end barfs with the code (generated by a third-party front-end):
define i64 @atomic_load_i64_other_address_space(i64 addrspace(1)* align 8 %ptr)
{
load_entry:
%val = load atomic i64, i64 addrspace(1)* %ptr acquire, align 8
ret i64 %val
}
define void @atomic_store_i64_other_address_space(i64 addrspace(1)* align 8
%ptr, i64 %value) {
store_entry:
store atomic i64 %value, i64 addrspace(1)* %ptr release, align 8
ret void
}
and command line:
$ llc < %s -mtriple=thumbv7-linux-gnueabihf
with error: "invalid bit-cast".
The problem is in ARMISelLowering.cpp::emitLoadLinked:
Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
where Addr is not in the default address space.
The questions are:
1. What is the semantics in this case?
2. Do we create the i8* on the same address space?
3. Do we even want to know about address spaces at that level?
If the answer to (3) is "yes", then (2) seems like a valid solution. But I may
be missing something obvious.</pre>
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