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<base href="https://bugs.llvm.org/">
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<body><table border="1" cellspacing="0" cellpadding="8">
<tr>
<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - Vector comparisons are not canonicalized"
href="https://bugs.llvm.org/show_bug.cgi?id=50605">50605</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>Vector comparisons are not canonicalized
</td>
</tr>
<tr>
<th>Product</th>
<td>libraries
</td>
</tr>
<tr>
<th>Version</th>
<td>trunk
</td>
</tr>
<tr>
<th>Hardware</th>
<td>PC
</td>
</tr>
<tr>
<th>OS</th>
<td>All
</td>
</tr>
<tr>
<th>Status</th>
<td>NEW
</td>
</tr>
<tr>
<th>Severity</th>
<td>enhancement
</td>
</tr>
<tr>
<th>Priority</th>
<td>P
</td>
</tr>
<tr>
<th>Component</th>
<td>Common Code Generator Code
</td>
</tr>
<tr>
<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
<tr>
<th>Reporter</th>
<td>dave@znu.io
</td>
</tr>
<tr>
<th>CC</th>
<td>llvm-bugs@lists.llvm.org
</td>
</tr></table>
<p>
<div>
<pre>The following input IR does not canonicalize consistently. Notably example_a_lt
optimized IR should be the same as example_a_ge. Similarly, example_b_le should
generate the same optimized IR as example_b_gt. The actual output with
top-of-tree LLVM follows the input IR:
define dso_local <16 x i32> @_Z12example_a_ltDv16_iS_S_(<16 x i32> %0, <16 x
i32> %1, <16 x i32> %2) #0 {
%4 = alloca <16 x i32>, align 64
%5 = alloca <16 x i32>, align 64
%6 = alloca <16 x i32>, align 64
store <16 x i32> %0, <16 x i32>* %4, align 64
store <16 x i32> %1, <16 x i32>* %5, align 64
store <16 x i32> %2, <16 x i32>* %6, align 64
%7 = load <16 x i32>, <16 x i32>* %4, align 64
%8 = icmp slt <16 x i32> %7, zeroinitializer
%9 = sext <16 x i1> %8 to <16 x i32>
%10 = load <16 x i32>, <16 x i32>* %5, align 64
%11 = load <16 x i32>, <16 x i32>* %6, align 64
%12 = icmp ne <16 x i32> %9, zeroinitializer
%13 = select <16 x i1> %12, <16 x i32> %10, <16 x i32> %11
ret <16 x i32> %13
}
; Function Attrs: noinline nounwind optnone uwtable mustprogress
define dso_local <16 x i32> @_Z12example_a_geDv16_iS_S_(<16 x i32> %0, <16 x
i32> %1, <16 x i32> %2) #0 {
%4 = alloca <16 x i32>, align 64
%5 = alloca <16 x i32>, align 64
%6 = alloca <16 x i32>, align 64
store <16 x i32> %0, <16 x i32>* %4, align 64
store <16 x i32> %1, <16 x i32>* %5, align 64
store <16 x i32> %2, <16 x i32>* %6, align 64
%7 = load <16 x i32>, <16 x i32>* %4, align 64
%8 = icmp sge <16 x i32> %7, zeroinitializer
%9 = sext <16 x i1> %8 to <16 x i32>
%10 = load <16 x i32>, <16 x i32>* %6, align 64
%11 = load <16 x i32>, <16 x i32>* %5, align 64
%12 = icmp ne <16 x i32> %9, zeroinitializer
%13 = select <16 x i1> %12, <16 x i32> %10, <16 x i32> %11
ret <16 x i32> %13
}
; Function Attrs: noinline nounwind optnone uwtable mustprogress
define dso_local <16 x i32> @_Z12example_b_leDv16_iS_S_(<16 x i32> %0, <16 x
i32> %1, <16 x i32> %2) #0 {
%4 = alloca <16 x i32>, align 64
%5 = alloca <16 x i32>, align 64
%6 = alloca <16 x i32>, align 64
store <16 x i32> %0, <16 x i32>* %4, align 64
store <16 x i32> %1, <16 x i32>* %5, align 64
store <16 x i32> %2, <16 x i32>* %6, align 64
%7 = load <16 x i32>, <16 x i32>* %4, align 64
%8 = icmp sle <16 x i32> %7, zeroinitializer
%9 = sext <16 x i1> %8 to <16 x i32>
%10 = load <16 x i32>, <16 x i32>* %5, align 64
%11 = load <16 x i32>, <16 x i32>* %6, align 64
%12 = icmp ne <16 x i32> %9, zeroinitializer
%13 = select <16 x i1> %12, <16 x i32> %10, <16 x i32> %11
ret <16 x i32> %13
}
; Function Attrs: noinline nounwind optnone uwtable mustprogress
define dso_local <16 x i32> @_Z12example_b_gtDv16_iS_S_(<16 x i32> %0, <16 x
i32> %1, <16 x i32> %2) #0 {
%4 = alloca <16 x i32>, align 64
%5 = alloca <16 x i32>, align 64
%6 = alloca <16 x i32>, align 64
store <16 x i32> %0, <16 x i32>* %4, align 64
store <16 x i32> %1, <16 x i32>* %5, align 64
store <16 x i32> %2, <16 x i32>* %6, align 64
%7 = load <16 x i32>, <16 x i32>* %4, align 64
%8 = icmp sgt <16 x i32> %7, zeroinitializer
%9 = sext <16 x i1> %8 to <16 x i32>
%10 = load <16 x i32>, <16 x i32>* %6, align 64
%11 = load <16 x i32>, <16 x i32>* %5, align 64
%12 = icmp ne <16 x i32> %9, zeroinitializer
%13 = select <16 x i1> %12, <16 x i32> %10, <16 x i32> %11
ret <16 x i32> %13
}
The current output IR after optimizations is:
define dso_local <16 x i32> @_Z12example_a_ltDv16_iS_S_(<16 x i32> %0, <16 x
i32> %1, <16 x i32> %2) local_unnamed_addr #0 {
%4 = icmp sgt <16 x i32> %0, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1,
i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
%5 = select <16 x i1> %4, <16 x i32> %2, <16 x i32> %1
ret <16 x i32> %5
}
; Function Attrs: nofree norecurse nosync nounwind readnone uwtable willreturn
mustprogress
define dso_local <16 x i32> @_Z12example_a_geDv16_iS_S_(<16 x i32> %0, <16 x
i32> %1, <16 x i32> %2) local_unnamed_addr #0 {
%4 = icmp slt <16 x i32> %0, zeroinitializer
%5 = select <16 x i1> %4, <16 x i32> %1, <16 x i32> %2
ret <16 x i32> %5
}
; Function Attrs: nofree norecurse nosync nounwind readnone uwtable willreturn
mustprogress
define dso_local <16 x i32> @_Z12example_b_leDv16_iS_S_(<16 x i32> %0, <16 x
i32> %1, <16 x i32> %2) local_unnamed_addr #0 {
%4 = icmp sgt <16 x i32> %0, zeroinitializer
%5 = select <16 x i1> %4, <16 x i32> %2, <16 x i32> %1
ret <16 x i32> %5
}
; Function Attrs: nofree norecurse nosync nounwind readnone uwtable willreturn
mustprogress
define dso_local <16 x i32> @_Z12example_b_gtDv16_iS_S_(<16 x i32> %0, <16 x
i32> %1, <16 x i32> %2) local_unnamed_addr #0 {
%4 = icmp slt <16 x i32> %0, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32
1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
%5 = select <16 x i1> %4, <16 x i32> %1, <16 x i32> %2
ret <16 x i32> %5
}</pre>
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