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      <base href="https://bugs.llvm.org/">
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    <body><table border="1" cellspacing="0" cellpadding="8">
        <tr>
          <th>Bug ID</th>
          <td><a class="bz_bug_link 
          bz_status_NEW "
   title="NEW - [X86] X86ISelLowering combineShiftLeft contains a transform that isn't undef safe."
   href="https://bugs.llvm.org/show_bug.cgi?id=50468">50468</a>
          </td>
        </tr>

        <tr>
          <th>Summary</th>
          <td>[X86] X86ISelLowering combineShiftLeft contains a transform that isn't undef safe.
          </td>
        </tr>

        <tr>
          <th>Product</th>
          <td>libraries
          </td>
        </tr>

        <tr>
          <th>Version</th>
          <td>trunk
          </td>
        </tr>

        <tr>
          <th>Hardware</th>
          <td>PC
          </td>
        </tr>

        <tr>
          <th>OS</th>
          <td>All
          </td>
        </tr>

        <tr>
          <th>Status</th>
          <td>NEW
          </td>
        </tr>

        <tr>
          <th>Severity</th>
          <td>enhancement
          </td>
        </tr>

        <tr>
          <th>Priority</th>
          <td>P
          </td>
        </tr>

        <tr>
          <th>Component</th>
          <td>Backend: X86
          </td>
        </tr>

        <tr>
          <th>Assignee</th>
          <td>unassignedbugs@nondot.org
          </td>
        </tr>

        <tr>
          <th>Reporter</th>
          <td>craig.topper@gmail.com
          </td>
        </tr>

        <tr>
          <th>CC</th>
          <td>craig.topper@gmail.com, llvm-bugs@lists.llvm.org, llvm-dev@redking.me.uk, pengfei.wang@intel.com, spatel+llvm@rotateright.com
          </td>
        </tr></table>
      <p>
        <div>
        <pre>This function contains this transform which increases the uses of V. This isn't
correct if V is undef or could become undef later.

  // Hardware support for vector shifts is sparse which makes us scalarize the  
  // vector operations in many cases. Also, on sandybridge ADD is faster than   
  // shl.                                                                       
  // (shl V, 1) -> add V,V                                                      
  if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))                             
    if (auto *N1SplatC = N1BV->getConstantSplatNode()) {                        
      assert(N0.getValueType().isVector() && "Invalid vector shift type");      
      // We shift all of the values by one. In many cases we do not have        
      // hardware support for this operation. This is better expressed as an
ADD                                                                             
      // of two values.                                                         
      if (N1SplatC->isOne())                                                    
        return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);                     
    } 


For i16/i32/i64 we can probably just use an isel pattern instead like we do for
scalar shift left. Not sure how to preserve i8.</pre>
        </div>
      </p>


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