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      <base href="https://bugs.llvm.org/">
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    <body><table border="1" cellspacing="0" cellpadding="8">
        <tr>
          <th>Bug ID</th>
          <td><a class="bz_bug_link 
          bz_status_NEW "
   title="NEW - wasm32: v128.load32_zero not used with equivalent pattern"
   href="https://bugs.llvm.org/show_bug.cgi?id=50434">50434</a>
          </td>
        </tr>

        <tr>
          <th>Summary</th>
          <td>wasm32: v128.load32_zero not used with equivalent pattern
          </td>
        </tr>

        <tr>
          <th>Product</th>
          <td>libraries
          </td>
        </tr>

        <tr>
          <th>Version</th>
          <td>trunk
          </td>
        </tr>

        <tr>
          <th>Hardware</th>
          <td>PC
          </td>
        </tr>

        <tr>
          <th>OS</th>
          <td>All
          </td>
        </tr>

        <tr>
          <th>Status</th>
          <td>NEW
          </td>
        </tr>

        <tr>
          <th>Severity</th>
          <td>enhancement
          </td>
        </tr>

        <tr>
          <th>Priority</th>
          <td>P
          </td>
        </tr>

        <tr>
          <th>Component</th>
          <td>Backend: WebAssembly
          </td>
        </tr>

        <tr>
          <th>Assignee</th>
          <td>unassignedbugs@nondot.org
          </td>
        </tr>

        <tr>
          <th>Reporter</th>
          <td>alex@crichton.co
          </td>
        </tr>

        <tr>
          <th>CC</th>
          <td>llvm-bugs@lists.llvm.org
          </td>
        </tr></table>
      <p>
        <div>
        <pre>Given this LLVM IR:



; ModuleID = 'foo.3a1fbbbh-cgu.0'
source_filename = "foo.3a1fbbbh-cgu.0"
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-wasi"

; Function Attrs: norecurse nounwind readonly willreturn
define dso_local <4 x i32> @v128_load32_zero(i32* nocapture readonly %a, <4 x
i32> %b) unnamed_addr #0 {
start:
  %_3 = load i32, i32* %a, align 4
  %_5.12.vec.insert.i.i = insertelement <4 x i32> <i32 poison, i32 0, i32 0,
i32 0>, i32 %_3, i32 0
  ret <4 x i32> %_5.12.vec.insert.i.i
}

attributes #0 = { norecurse nounwind readonly willreturn "target-cpu"="generic"
"target-features"="+simd128" }




this doesn't currently optimize to use the `v128.load32_zero` intrinsic, it
requires using the `llvm.wasm.load32.zero` intrinsic. While not super
problematic it'd be nice if this equivalent pattern was recognized because it'd
allow easy configuration of the alignment on `v128.load32_zero` since it
happens via the `load` instruction separately.</pre>
        </div>
      </p>


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