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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [MCA] In-order pipeline does not terminate for some AMDGPU instructions"
href="https://bugs.llvm.org/show_bug.cgi?id=49712">49712</a>
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<th>Summary</th>
<td>[MCA] In-order pipeline does not terminate for some AMDGPU instructions
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<th>Product</th>
<td>tools
</td>
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<th>Version</th>
<td>trunk
</td>
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>All
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<th>Status</th>
<td>NEW
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<th>Severity</th>
<td>normal
</td>
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>llvm-mca
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>andrew.savonichev@gmail.com
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<th>CC</th>
<td>andrea.dibiagio@gmail.com, llvm-bugs@lists.llvm.org, matthew.davis@sony.com
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<pre>MCA does not terminate for AMDGPU/gfx10-double.s:
; FIXME: This instructions sends llvm-mca into an infinite loop
;v_div_scale_f64 v[0:1], vcc_lo, v[0:1], v[0:1], v[0:1]
The problem is that the instruction has 2 uops, and the processor's IssueWidth
is 1.
InOrderIssueStage treats IssueWidth as the maximum number of uops that can be
issued in one cycle. On the other hand, the documentation for MCSchedModel says
that IssueWidth is the maximum number of *instructions*.</pre>
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