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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [AArch64/FastIsel] Misoptimization of sext from function argument in the presence of spills."
href="https://bugs.llvm.org/show_bug.cgi?id=49357">49357</a>
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<th>Summary</th>
<td>[AArch64/FastIsel] Misoptimization of sext from function argument in the presence of spills.
</td>
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<th>Product</th>
<td>libraries
</td>
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<th>Version</th>
<td>trunk
</td>
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<th>Hardware</th>
<td>Macintosh
</td>
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<th>OS</th>
<td>MacOS X
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<th>Status</th>
<td>NEW
</td>
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<th>Severity</th>
<td>enhancement
</td>
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>Backend: AArch64
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>keno@alumni.harvard.edu
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<th>CC</th>
<td>arnaud.degrandmaison@arm.com, llvm-bugs@lists.llvm.org, smithp352@googlemail.com, Ties.Stuij@arm.com
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<p>
<div>
<pre>Created <span class=""><a href="attachment.cgi?id=24573" name="attach_24573" title="Testcase showing the issue.">attachment 24573</a> <a href="attachment.cgi?id=24573&action=edit" title="Testcase showing the issue.">[details]</a></span>
Testcase showing the issue.
Consider the attached testcase.ll, reduced from a downstream issue report at
<a href="https://github.com/JuliaLang/julia/issues/39823">https://github.com/JuliaLang/julia/issues/39823</a>.
The relevant snippet of the testcase is:
```
define nonnull {}* @julia_f_1854(i32 signext %0) #0 {
[snip]
call void inttoptr (i64 4342098656 to void ()*)()
[snip]
%10 = sext i32 %0 to i64
%11 = icmp slt i64 %10, 0
```
When run as `llc -mtriple arm64-apple-darwin20.0.0 -mcpu apple-a12
-code-model=small -O0 -fast-isel -o - testcase.ll`, the produced assembly is in
relevant part:
```
str w0, [sp, #8] ; 4-byte Folded Spill
blr x8
ldr w9, [sp, #8] ; 4-byte Folded Reload
[snip]
mov x8, x9
cmp x8, #0
```
Note that the sext got isel'ed to a `mov x8, x9`. This is because of
fast isel decided at [1] that this sext did not need an actual instruction
because of the arguments signext attribute. However, the implementation does
not work, because upper bits of the SUBREG_TO_REG'd register are undefined and
subsequent passes may clobber them (e.g. as in this case by a stack spill).
[1]
<a href="https://github.com/llvm/llvm-project/blob/2c56776a319edf33505ca6c7f9be59657cdaf52b/llvm/lib/Target/AArch64/AArch64FastISel.cpp#L4598-L4618">https://github.com/llvm/llvm-project/blob/2c56776a319edf33505ca6c7f9be59657cdaf52b/llvm/lib/Target/AArch64/AArch64FastISel.cpp#L4598-L4618</a></pre>
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