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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - Fuse v128.load64_zero + iXX.widen_low into Load-and-Extend"
href="https://bugs.llvm.org/show_bug.cgi?id=49210">49210</a>
</td>
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<th>Summary</th>
<td>Fuse v128.load64_zero + iXX.widen_low into Load-and-Extend
</td>
</tr>
<tr>
<th>Product</th>
<td>libraries
</td>
</tr>
<tr>
<th>Version</th>
<td>trunk
</td>
</tr>
<tr>
<th>Hardware</th>
<td>All
</td>
</tr>
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<th>OS</th>
<td>All
</td>
</tr>
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<th>Status</th>
<td>NEW
</td>
</tr>
<tr>
<th>Severity</th>
<td>enhancement
</td>
</tr>
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<th>Priority</th>
<td>P
</td>
</tr>
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<th>Component</th>
<td>Backend: WebAssembly
</td>
</tr>
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<th>Assignee</th>
<td>tlively@google.com
</td>
</tr>
<tr>
<th>Reporter</th>
<td>maratek@gmail.com
</td>
</tr>
<tr>
<th>CC</th>
<td>llvm-bugs@lists.llvm.org
</td>
</tr></table>
<p>
<div>
<pre>Even though x86 SSE4 provides load-and-extend instructions (PMOVSXxx/PMOVZXxx),
it don't provide the corresponding intrinsics. Commonly, these instruction
forms are exposed as a combination of 8-byte load (which implicitly zeroes the
upper 8 bytes) and conversion intrinsics, e.g.
_mm_cvtepi16_epi32(_mm_loadl_epi64(ptr)). When such codes are cross-compiled to
x86 using Emscripten's nmmintrin.h header, they will generate two WebAssembly
SIMD instructions, v128.load64_zero and i32x4.widen_low_i16x8_s, which would
subsequently lower into two x86 instructions by a WAsm engine. LLVM should
learn to fuse v128.load64_zero + i32x4.widen_low_i16x8_s into v128.load16x4_s,
so that codes cross-compiled from x86 SSE4 intrinsics generate the same
instructions in a WAsm engine as they do in native compilation.</pre>
</div>
</p>
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