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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [llvm-mca] Accuracy regression for independent r/w operations (Skylake, Zen+)"
href="https://bugs.llvm.org/show_bug.cgi?id=45793">45793</a>
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<th>Summary</th>
<td>[llvm-mca] Accuracy regression for independent r/w operations (Skylake, Zen+)
</td>
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<th>Product</th>
<td>tools
</td>
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<th>Version</th>
<td>trunk
</td>
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>Linux
</td>
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<th>Status</th>
<td>NEW
</td>
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<th>Severity</th>
<td>normal
</td>
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<th>Priority</th>
<td>P
</td>
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<th>Component</th>
<td>llvm-mca
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>fabian.ritter@cs.uni-saarland.de
</td>
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<th>CC</th>
<td>andrea.dibiagio@gmail.com, llvm-bugs@lists.llvm.org, matthew.davis@sony.com
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<div>
<pre>Created <span class=""><a href="attachment.cgi?id=23440" name="attach_23440" title="Archive containing the above instruction sequence and a C program to measure its throughput.">attachment 23440</a> <a href="attachment.cgi?id=23440&action=edit" title="Archive containing the above instruction sequence and a C program to measure its throughput.">[details]</a></span>
Archive containing the above instruction sequence and a C program to measure
its throughput.
Starting with Release 9 and up to today's trunk, there is a regression in
llvm-mca's prediction accuracy for sequences of independent instructions that
read and write memory.
Both x86 architectures that I tried, Intel's Skylake and AMD's Zen+, are
subject to this.
Consider the following example:
# LLVM-MCA-BEGIN
addq $44, 64(%r14)
addq $44, 128(%r14)
addq $44, 192(%r14)
addq $44, 256(%r14)
addq $44, 320(%r14)
addq $44, 384(%r14)
addq $44, 448(%r14)
addq $44, 512(%r14)
addq $44, 576(%r14)
addq $44, 640(%r14)
# LLVM-MCA-END
Measurements on my Skylake machine (as performed with the attached C program)
as well as IACA 3.0 and llvm-mca from Release 8 agree that this sequence
executes in 10 cycles (Total Cycles: 1009, since the memory offsets ensure that
the accesses are independent).
>From Release 9 on, llvm-mca reports 70 cycles (Total Cycles: 7003), maybe
because the instructions are falsely classified as dependent.
Zen+ shows a similar behavior.
This is not specific to the `add` instruction or the access width: Other r/w
instructions and all other access widths show the same behavior.
To reproduce, use the attached `add.s` as input for llvm-mca with the flags
`-march=x86-64` and `-mcpu=skylake` or `-mcpu=znver1`. The results for "Total
Cycles" will differ between Release 8 and later releases.
To verify that IACA agrees with Release 8, assemble `add.s` with your favorite
compiler/assembler and hand the result to IACA.
To verify the measurements on an actual machine, compile `add.c` with your
favorite C compiler and execute the result. It will print the required cycles
(results may depend on system load and configuration, adjust the frequency in
the source as necessary).</pre>
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