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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - RISC-V DataLayout is wrong which causes many optimizations to not work on RISC-V"
href="https://bugs.llvm.org/show_bug.cgi?id=45708">45708</a>
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<th>Summary</th>
<td>RISC-V DataLayout is wrong which causes many optimizations to not work on RISC-V
</td>
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<th>Product</th>
<td>new-bugs
</td>
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<th>Version</th>
<td>trunk
</td>
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<th>Hardware</th>
<td>All
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<th>OS</th>
<td>All
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<th>Status</th>
<td>NEW
</td>
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<th>Severity</th>
<td>enhancement
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>new bugs
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>heikki.kultala@gmail.com
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<th>CC</th>
<td>htmldeveloper@gmail.com, llvm-bugs@lists.llvm.org
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<p>
<div>
<pre>The RV32I and RV64I Base ISAs supports 8-bit and 16-bit memory operations, AND
they support unaligned memory operations.
However, on LLVM
RISCV32 data layout is just "e-m:e-p:32:32-i64:64-n32-S128",
and RISCV64 data layout is just "e-m:e-p:64:64-i64:64-i128:128-n64-S128".
These lacks information about 8- and 16-bit data types, and also the alignment
for 32 and 64 bit memory accesses is wrong.
Because the data layout forces aligned memory accesses, the backend generates
very slow code consisting of multiple narrower accesses when it cannot prove
that a memory access is aligned.
And the total lack of information about 8-bit and 16-bit accesses in the data
layout makes clang think 8-bit and 16-bit types or memory accesses are not
legal, which prevents some optimizations from working, for example
-ffine-grained-bitfield-accesses fails to generate 8-bit or 16-bit accesses
because there is a check that it only generates legal loads.</pre>
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