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<base href="https://bugs.llvm.org/">
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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [GlobalISel] Assertion failure after IRTranslator translates complex ConstantExpr"
href="https://bugs.llvm.org/show_bug.cgi?id=45576">45576</a>
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<th>Summary</th>
<td>[GlobalISel] Assertion failure after IRTranslator translates complex ConstantExpr
</td>
</tr>
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<th>Product</th>
<td>libraries
</td>
</tr>
<tr>
<th>Version</th>
<td>trunk
</td>
</tr>
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>Linux
</td>
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<th>Status</th>
<td>NEW
</td>
</tr>
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<th>Severity</th>
<td>enhancement
</td>
</tr>
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>GlobalISel
</td>
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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</tr>
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<th>Reporter</th>
<td>jay.foad@gmail.com
</td>
</tr>
<tr>
<th>CC</th>
<td>llvm-bugs@lists.llvm.org, quentin.colombet@gmail.com
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<pre>Created <span class=""><a href="attachment.cgi?id=23375" name="attach_23375" title="test case">attachment 23375</a> <a href="attachment.cgi?id=23375&action=edit" title="test case">[details]</a></span>
test case
With the attached test case I get:
$ llc -march=aarch64 -global-isel -verify-machineinstrs < r.ll
# After IRTranslator
# Machine code for function main: IsSSA, TracksLiveness
bb.1 (%ir-block.0):
%6:_(s32) = G_CONSTANT i32 -1
%5:_(p0) = G_INTTOPTR %6:_(s32)
%7:_(p0) = G_GLOBAL_VALUE @var
%4:_(s1) = G_ICMP intpred(eq), %5:_(p0), %7:_
%3:_(s32) = G_ZEXT %4:_(s1)
%2:_(s32) = COPY %3:_(s32)
%0:_(s32) = COPY %1:_(s32)
$w0 = COPY %0:_(s32)
RET_ReallyLR implicit $w0
# End machine code for function main.
*** Bad machine code: Reading virtual register without a def ***
- function: main
- basic block: %bb.1 (0x90f1c88)
- instruction: %0:_(s32) = COPY %1:_(s32)
- operand 1: %1:_
LLVM ERROR: Found 1 machine code errors.
PLEASE submit a bug report to <a href="https://bugs.llvm.org/">https://bugs.llvm.org/</a> and include the crash
backtrace.
I think the problem is in IRTranslator::translate(const Constant &C, Register
Reg). If C is a ConstantExpr it does this:
} else if (auto CE = dyn_cast<ConstantExpr>(&C)) {
switch(CE->getOpcode()) {
#define HANDLE_INST(NUM, OPCODE, CLASS)
\
case Instruction::OPCODE:
\
return translate##OPCODE(*CE, *EntryBuilder.get());
#include "llvm/IR/Instruction.def"
... which completely ignores the "Reg" argument and generates the result into
some other register of its choosing. I can't see how this has ever worked.</pre>
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