<html>
    <head>
      <base href="https://bugs.llvm.org/">
    </head>
    <body><table border="1" cellspacing="0" cellpadding="8">
        <tr>
          <th>Bug ID</th>
          <td><a class="bz_bug_link 
          bz_status_NEW "
   title="NEW - [entry values] ARM isCopyInstrImpl incorrect for VMOVS"
   href="https://bugs.llvm.org/show_bug.cgi?id=45025">45025</a>
          </td>
        </tr>

        <tr>
          <th>Summary</th>
          <td>[entry values] ARM isCopyInstrImpl incorrect for VMOVS
          </td>
        </tr>

        <tr>
          <th>Product</th>
          <td>libraries
          </td>
        </tr>

        <tr>
          <th>Version</th>
          <td>trunk
          </td>
        </tr>

        <tr>
          <th>Hardware</th>
          <td>PC
          </td>
        </tr>

        <tr>
          <th>OS</th>
          <td>All
          </td>
        </tr>

        <tr>
          <th>Status</th>
          <td>NEW
          </td>
        </tr>

        <tr>
          <th>Severity</th>
          <td>normal
          </td>
        </tr>

        <tr>
          <th>Priority</th>
          <td>P
          </td>
        </tr>

        <tr>
          <th>Component</th>
          <td>Backend: ARM
          </td>
        </tr>

        <tr>
          <th>Assignee</th>
          <td>unassignedbugs@nondot.org
          </td>
        </tr>

        <tr>
          <th>Reporter</th>
          <td>vsk@apple.com
          </td>
        </tr>

        <tr>
          <th>CC</th>
          <td>llvm-bugs@lists.llvm.org, smithp352@googlemail.com, Ties.Stuij@arm.com
          </td>
        </tr></table>
      <p>
        <div>
        <pre>We get the following assertion failure when building ARM code:

Assertion failed: (!TRI->isSuperOrSubRegisterEq(Reg, DestReg) &&
"TargetInstrInfo::describeLoadedValue can't describe super- or " "sub-regs for
copy instructions"

The following instruction is passed to TargetInstrInfo::describeLoadedValue:

$s1 = VMOVS killed $s21, 14, $noreg, implicit-def $d0

ARMBaseInstrInfo::isCopyInstrImpl reports that this is a copy:

```
  Optional<DestSourcePair> isCopyInstr(const MachineInstr &MI) const {
    if (MI.isCopy()) {
      return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
    }
    return isCopyInstrImpl(MI); // <- Reached.
  }

  =>

  if (!MI.isMoveReg() ||
      (MI.getOpcode() == ARM::VORRq &&
       MI.getOperand(1).getReg() != MI.getOperand(2).getReg()))
    return None;
  return DestSourcePair{MI.getOperand(0), MI.getOperand(1)}; // <- Reached.
```

According to TRI, llvm think that s1 is a sub-register of s21. I'm not sure
that's what the docs say:
<a href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0344k/ch13s03s02.html">http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0344k/ch13s03s02.html</a>
(this makes it look like s{0..31} are independent single-word registers).

Regardless, istm that ARMBaseInstrInfo::isCopyInstrImpl should be taking a
whitelisting approach, not a blacklist. I.e. we should not allow non-copy
instructions we haven't explicitly handled be treated as copies.</pre>
        </div>
      </p>


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